Multiple sequentially transferrable stackpointers in a data proc

Details Multiple sequentially transferrable stackpointers in a data proc Multiple sequentially transferrable stackpointers in a data proc

1995-03-22

1996-10-15

Bowler, Alyssa H.

Boots, shoes, and leggings

3642318, 3642443, 3642477, 364DIG1, G06F 938

Patent

active

055663079

ABSTRACT:
This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

REFERENCES:
patent: 4025771 (1977-05-01), Lynch, Jr. et al.
patent: 4270182 (1981-05-01), Tanakura et al.
patent: 4399507 (1983-08-01), Cosgrove et al.
patent: 4697233 (1987-09-01), Scheuneman et al.
Wakerly, John F., "Microcomputer Architecture and Programming" John Wiley & Sons, Inc., 1981.

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