Multiple sequentially transferrable stackpointers in a data proc

Details Multiple sequentially transferrable stackpointers in a data proc Multiple sequentially transferrable stackpointers in a data proc

1990-04-09

1990-11-27

Anderson, Lawrence E.

Boots, shoes, and leggings

3642443, 3642318, G06F 938

Patent

active

049741586

ABSTRACT:
This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

REFERENCES:
patent: 4025771 (1977-05-01), Lynch
patent: 4270181 (1981-05-01), Tanakura
patent: 4697233 (1987-09-01), Scheuneman et al.
"Microcomputer Architecture and Programming", John F. Wakerly (1981), John Wiley & Sons.

Affiliated with

Also associated with

Rating

Multiple sequentially transferrable stackpointers in a data proc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple sequentially transferrable stackpointers in a data proc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple sequentially transferrable stackpointers in a data proc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1036765