Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1998-07-07
2001-11-06
Grant, William (Department: 2121)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S002000, C700S116000, C700S121000, C700S218000
Reexamination Certificate
active
06314332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device test apparatus of a plurality of semiconductor devices, more particularly, to a semiconductor device test apparatus for performing an electric characteristic test of each of the plurality of semiconductor devices grouped into one or more lots using a plurality of testers. Also, the present invention relates to a semiconductor device test apparatus for performing an electric characteristic test of a plurality of kinds of lots of a plurality of semiconductor devices, using a plurality of testers.
2. Description of the Related Art
As a conventional semiconductor device test apparatus, a semiconductor device test apparatus is proposed in, for example, Japanese Laid Open Patent Disclosure (JP-A-Heisei 5-26959). In the semiconductor device test apparatus, there is not necessity of the modification of design of a test head and a handler main section even if the number of semiconductor devices to be measured by a tester at the same time increases.
FIG. 1
is a diagram for illustrating the structure of the semiconductor device test apparatus proposed in the above Japanese Laid Open Patent Disclosure (JP-A-Heisei 5-26959).
FIGS. 3A
to
3
B are expanded perspective views for illustrating a main section of the test head of the semiconductor device test apparatus.
In
FIG. 1
, the semiconductor device test apparatus is composed of a tester
601
, test heads
602
, cables
603
, handler main sections
607
, a loader section
608
, a pallet transporting section
609
and an unloader section
610
. The tester
601
performs an electric characteristic test of the semiconductor devices. The test heads
602
are electrically connected with the tester
601
through the cables
603
. The plurality of handler main sections
607
are arranged in parallel to be connected to the test heads
602
. The loader section
608
transfers the semiconductor devices from interprocess
605
trays to the pallets
604
. Each of the interprocess trays
605
is a unit for transporting the semiconductor devices
401
between this apparatus and another apparatus. The loader section
608
sets pallets
604
in which the semiconductor devices before the electric characteristic test are located therein. The pallet transporting section
609
transports the pallets
604
supplied from the loader section
608
to each of the handler main sections
607
. After the electric characteristic test, the pallets
604
are transported from each of the handler main sections
607
to the unloader section
609
by the pallet transporting section
609
. The unloader section accommodates the pallets
604
which contain the semiconductor devices after the electric characteristic test.
Also, in
FIGS. 3A and 3B
, a reference number
402
denotes a test socket for the semiconductor device
401
to be inserted and held in case of the electric characteristic test. A reference number
403
denotes a test board for the plurality of test sockets
402
to be mounted for electric connection with the test head
602
.
First, the transporting state of the semiconductor devices
401
and the operation of each section of the apparatus will be described with reference to FIG.
1
and
FIGS. 3A and 3B
.
The interprocess tray
605
containing one lot of semiconductor devices
401
before the electric characteristic test is set in the loader section
608
. Then, the semiconductor devices
401
are moved from the interprocess tray
605
to the pallets
604
for apparatus exclusive use. After that, the pallets
604
are sent out to the pallet transporting section
609
.
The pallet transporting section
609
transports the pallets
604
to each of the handler main sections
607
in order. In each handler main section
607
, the semiconductor devices
401
in the pallet
604
are electrically connected with the test board
403
fixed on the test head
602
. Then, the electric characteristic test is performed by the tester
601
through the cable
603
.
Next, the pallet
604
with the semiconductor devices after the electric characteristic test is sent out from the handler main section
607
to the pallet transporting section
609
. Subsequently, the pallet
604
is transported to the unloader section
610
.
In the unloader section
610
, the semiconductor devices
401
after the electric characteristic test which are provided in each of the pallets
604
are classified and accommodated into the interprocess trays
605
which are prepared for every defective product and category, based on quality information and a category mechanism (Hereinafter, two kinds of data are referred to as a “test resultant data”) which are transmitted from the handler main section.
The above description is about the flow of the semiconductor devices
401
for the once electric characteristic test by the tester
601
and the operation of each section. This operation is repeated until all the pallets
604
in the loader section
608
are tested and accommodated in the unloader section
610
.
Next, the processing flow to realize the above-mentioned operation will be explained.
FIGS. 2A
to
2
F are diagrams to describe the details of the processing flow. It should be noted that the processing flow shown in
FIGS. 2A
to
2
F is not disclosed in the above Japanese Laid Open Patent Disclosure (JP-A-Heisei 5-26959). Therefore,
FIGS. 2A
to
2
F show the processing flow considered in such a manner that the semiconductor device test apparatus shown in
FIG. 1
functions in the actual test process.
Steps
700
to
705
: are a preparation procedure of each of the sections (the loader section
608
and the tester
601
) of the apparatus by hand work.
Steps
710
to
720
: are a control procedure for separation of the pallets
604
in the loader section
608
and the transporting operation to each of the handler sections
607
.
Steps
730
, and
740
to
742
: are a handling operation procedure of the pallets
604
and the semiconductor devices
401
in the pallet transporting section
609
and each of the handler sections
607
.
Steps
760
to
766
: are a control procedure from the electric characteristic test by the tester
601
to the information transmission to the handler sections
607
.
Steps
770
to
778
: are a control procedure from an operation to collect the semiconductor devices
401
after the electric characteristic test from the test head
602
to the information transmission to deliver the next un-measured pallet
604
.
Step
780
: is a control procedure from the collection of the pallets
604
by the pallet transporting section
609
and the delivery to the unloader section
610
.
Steps
790
to
794
: are a control procedure in which the semiconductor devices
401
are accommodated from the pallets
604
and classified into interprocess trays
605
based on classification information.
In the case that the semiconductor devices
401
after the electric characteristic test are classified and accommodated in the step
794
, it is recognized based on the order of the pallets
604
that the pallet
604
is processed by which one of the handler sections
607
. For instance, in case of the structure shown in
FIG. 1
, the numbers are allocated as
1
,
2
,
3
,
4
from the handler section
607
near the unloader section
610
. The judgement of the classification is performed based on the numbers, and the quality information and the category information of each of the semiconductor devices
401
which are transmitted from each of the handler sections
607
.
Also, the lot is set in the loader section
608
is 1 lot. Accordingly, the semiconductor devices
401
tested by a single tester
601
are supplied for one lot.
When the electric characteristic test is performed to a DRAM (random access memory) as the semiconductor device to be tested, the tester (memory tester)
601
is possible to test 64 DRAMs at maximum at the same time, if the DRAM is a single bit I/O type.
In case of the above conventional apparatus, 16 semiconductor devices per the handler section (test head)
Grant William
NEC Corporation
Rao Sheela
Sughrue Mion Zinn Macpeak & Seas, PLLC
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