Multiple sampling sample and hold architectures

Details Multiple sampling sample and hold architectures Multiple sampling sample and hold architectures

2006-03-08

2008-09-09

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S337000, C327S554000, C327S094000, C327S096000

Reexamination Certificate

active

07423458

ABSTRACT:
A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.

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patent: 2004152329 (2004-05-01), None
Waltari et al., “A 10-Bit 220-MSample/s CMOS Sample-and-Hold Circuit” Electronic Circuit Design Laboratory, Helsinki University of Technology, 1998, pp. 1253-1256.

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