Multiple reference clock synthesizer

Details Multiple reference clock synthesizer Multiple reference clock synthesizer

2007-01-16

2007-01-16

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synthesizer

C327S105000, C377S048000

Reexamination Certificate

active

11095066

ABSTRACT:
A clock synthesizer for dividing a source clock by N.R including a logic circuit, a delay line, a select circuit, an accumulator, and a clock divider circuit. The logic circuit divides N.R by 2Mto get NNEW.RNEW in which NNEW is zero and RNEW is at least 0.5. The delay line receives a first clock and has multiple delay taps, where the first clock is based on the source clock. The select circuit selects the delay taps based on a tap select value and provides a delayed clock. The accumulator adds RNEW for each cycle of the delayed clock and performs a modulo function on a sum value to generate the tap select value. The clock divider circuit transitions an output clock based on selected transitions of the delayed clock, which is achieved by dividing the first clock or the delayed clock by 2M−1.

REFERENCES:
patent: 5195044 (1993-03-01), Wischermann
patent: 5977805 (1999-11-01), Vergnes et al.
patent: 6459753 (2002-10-01), Verlinden
patent: 6794913 (2004-09-01), Stengel
patent: 6998928 (2006-02-01), Stengel et al.
Dorin Emil Calbaza and Yvon Savaria,Direct Digital Frequency Synthesis of Low-Jitter Clocks,IEEE Journal of Solid-State Circuits, vol. 36, No. 3 Mar. 2001 pp. 570-572.

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