Multiple range current measurement system with low power...

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Plural ranges – scales or registration rates

Reexamination Certificate

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C324S12300R, C324S523000

Reexamination Certificate

active

06603301

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
Not Applicable
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiple range current measuring system and more particularly to a current measuring system having a low power loss, fast settling time and low common mode voltage error.
2. Description of the Related Art
Conventional dual range current measurement circuits include a parallel shunt and a series shunt configuration, as shown in
FIGS. 1 and 2
, respectively. These configurations have several disadvantages that warrant the need for an alternate topology to perform multiple range current measurements. These conventional circuits will be discussed along with their relative disadvantages.
Referring to
FIG. 1
, a current I
1
is produced by an external source of current and is directed through measurement shunt resistance R
H
or R
L
by closing switch S
H
or S
L
. Switches S
H
and S
L
are independently operated by external controls, which are not shown. Where a high range measurement is desired, switch S
H
is closed allowing current I
1
to flow through R
H
to circuit common. With switch S
H
closed, a voltage drop develops across R
H
at the noninverting (+) and inverting (−) input terminals of high input impedance, fixed gain instrumentation amplifier U
2
. The gain of amplifier U
2
is set to obtain a convenient volt per amp scale factor output voltage versus input current I
1
. Given the direction of current flow and the orientation of the input terminals of the amplifier U
2
as shown in
FIG. 1
, a positive voltage (I
monH
), with reference to circuit common, will result at the output of the instrumentation amplifier U
2
.
Switching from a high range measurement to a low range measurement in a minimally disruptive way requires closing switch S
L
in a make before break fashion and then opening switch S
H
. By measuring a voltage drop across shunt R
L
with instrumentation amplifier U
1
, a voltage, I monitor low (I
monL
) is developed with respect to the circuit common. Capacitor C
L
connected in parallel with relatively high value shunt resistance R
L
, serves to filter noise and to provide a low dynamic impedance between the external source of current and circuit common. Using this measurement scheme, the value of shunt R
L
will be greater than the value of shunt R
H
to allow for more sensitive measurements of low level currents. In the arrangement of
FIG. 1
, either I
monH
or I
monL
is available, but not both simultaneously.
The series shunt arrangement operates in a manner somewhat similar to the operation of the parallel shunt configuration shown in FIG.
1
. Referring now to
FIG. 2
, a current I
1
flows from an external source through a resistor R
H
where a voltage drop is developed. This voltage drop is impressed upon the inverting (−) and non-inverting (+) terminals of the high input impedance, fixed gain instrumentation amplifier U
2
producing the I
monH
voltage with reference to the circuit common. With I
monH
active and I
monL
not active a switch S
L
is closed across a shunt resistance R
L
, allowing large currents to flow without a substantial voltage drop. To perform a low range measurement, the switch S
L
is opened allowing current flow through the shunt resistance R
L
, permitting a low range measurement in a manner similar to the parallel arrangement of FIG.
1
. During a low range measurement, current is also flowing through the resistor R
H
, and thus the signal I
monH
is always available.
An alternate arrangement of the series shunt topology is shown with broken lines in FIG.
2
. In the alternate arrangement, the switch S
L
is not used and a dual polarity shunt regulator SR
1
is placed across R
L
. A simple example of such a shunt regulator is shown as diodes D
1
and D
2
. The configuration of
FIG. 2
provides a bypass for R
L
without external switch control.
The series and parallel shunt configurations share disadvantages that warrant a need for a new topology. In both the series and parallel shunt arrangements, the insertion impedance of the measurement circuit may be larger than desired and the insertion impedance will change abruptly as various shunts are switched in and out of the circuit. Switching between measurement shunts contributes to settling time problems in the measuring circuit and causes disturbances in the external current flow due to the change in impedance of the measuring circuit.
The use of either solid state or mechanical relays in the circuits of FIG.
1
and
FIG. 2
presents several areas of concern. In particular, complex switch control is required to change from one-measurement range to another. Switch control does not occur automatically and can result in shunts being overpowered if a high current is not diverted around the shunt R
L
. In addition, if mechanical switches are used, contact bounce and lifetime become an issue. Solid state switches are prone to leakage and surge currents can damage solid state or mechanical switches.
The capacitor C
L
, which is placed in parallel with the resistor R
L
in both topologies, results in a long settling time constant, increasing the time required to take an accurate reading of the I
monL
voltage signal. The capacitor C
L
may also cause measurement errors by leaking current around the shunt resistor R
L
which is in parallel with the capacitor C
L
in the circuits of
FIGS. 1 and 2
.
In the case of the series shunt arrangement that utilizes the shunt regulator SR
1
, significant power may be dissipated in the resistor R
L
and shunt regular SR
1
, especially for high values of current. Additionally, leakage currents in the shunt regulator SR
1
can cause measurement errors in the I
monL
signal.
SUMMARY OF THE INVENTION
The present invention is a multi-range measuring circuit for measuring a flow of electrical current. An in-line sensor outputs a first signal proportional to the current and having a first scale factor. An amplifier circuit is serially connected with the in-line sensor and outputs a second signal having a second scale factor proportional to the current. A bypass circuit bypasses a portion of the input current around the amplifier circuit at values of the input current where the amplifier circuit is non-linear. The in-line sensor may be a resistor.
The bypass circuit comprises one of a P-type MOSFET, an N-type MOSFET or a P-type MOSFET parallel connected with an N-type MOSFET. The amplifier circuit comprises an inverting amplifier serially connected with a non-inverting amplifier and the non-inverting amplifier outputs the second signal. A control signal to operate the bypass circuit is output by a deadband circuit which is connected to the inverting amplifier. The deadband circuit is interposed between the output of the inverting amplifier and the bypass circuit. The deadband circuit passes the control signal where a value of the control signal is greater than a first predetermined value or less than a second predetermined value and rejects the control signal where the value of the control signal is intermediate the first and second predetermined values. The inverting amplifier operates in a first control loop where the deadband circuit rejects the control signal and operates in a second control loop where the deadband circuit passes the control signal.
The amplifier circuit comprises a summing node which receives the input current and the inverting amplifier is connected to the summing node. The non-inverting amplifier is connected to an output of the inverting amplifier and a feedback resistor is connected between an output of the non-inverting amplifier and the summing node, to regulate the second signal to be proportional to the current and according to the second scale factor. The deadband circuit comprises, for example, a diode network which determines the respective predetermined positive and negative values and the diode network comprises a plurality of series connected junction diodes.


REFERENCES:
patent: 3818247 (1974-06-01), Chambers et al.
patent: 4199799 (1980-04-

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