Multiple pulse delay processor

Details Multiple pulse delay processor Multiple pulse delay processor

1990-04-13

1991-04-02

Barron, Jr., Gilberto

Communications: directive radio wave systems and devices (e.g.,

Testing or calibrating of radar system

By simulation

G01S 740

Patent

active

050050176

ABSTRACT:
A transmit pulse delay processor for simulating delayed radar reflections from a target and a method for simulating delayed radar reflections. The pulse delay process utilizes a counter, an adder, a FIFO and a comparator. The pulse delay processor maintains input pulse width and features a programmable delay. The depth selected for the FIFO determines the number of transmit pulses that can be simultaneously delayed. The frequency of the resolution clock clocking the counter and the number of bits in the counter can be selected both to accommodate the length of delay required and to achieve better output pulse accuracy. The pulse delay processor has various applications, but is particularly useful in radar simulation where multiple input pulses must be simultaneously delayed.

REFERENCES:
patent: H513 (1988-08-01), Dunne et al.
patent: 4292634 (1981-09-01), Wu et al.
patent: 4450447 (1984-05-01), Zebker et al.
patent: 4635061 (1987-01-01), Lepere et al.
patent: 4794543 (1988-12-01), Enein et al.
patent: 4879561 (1989-11-01), Inkol

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