Multiple programming of spare memory region for nonvolatile...

Details Multiple programming of spare memory region for nonvolatile... Multiple programming of spare memory region for nonvolatile...

2008-05-23

2010-06-01

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185200

Reexamination Certificate

active

07729169

ABSTRACT:
Structures, methods, and systems for multiple programming of spare memory region for nonvolatile memory are disclosed. In one embodiment, a nonvolatile memory system comprises a main memory cell array, a spare memory cell array, and a memory controller that divides the spare memory cell array into at least a first region and a second region. The system further comprises a selection module for selecting the main memory cell array and the first region to write data and the first reference cell to write first reference data associated with the data during an initial data writing operation and for selecting the second region to write additional data and the second reference cell to write second reference data associated with the additional data during an additional data writing operation.

REFERENCES:
patent: 2004087047 (2004-03-01), None

Affiliated with

Also associated with

Rating

Multiple programming of spare memory region for nonvolatile... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple programming of spare memory region for nonvolatile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple programming of spare memory region for nonvolatile... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4203710