Electrical computers and digital processing systems: multicomput – Multicomputer data transferring via shared memory
Reexamination Certificate
1998-12-14
2002-04-23
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: multicomput
Multicomputer data transferring via shared memory
C709S208000
Reexamination Certificate
active
06377979
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to multiple-processor systems that transfer data between a master system and a slave system via a shared memory.
2. Description of the Related Art
A multiple-processor system that uses a dual-port memory (shared memory) having two input/output ports to transfer data between two central processing units (CPUs) is disclosed in, for example, Japanese Unexamined Patent Publication No. 8-161283. As shown in
FIG. 5
, in a multiple-processor system Z
0
of the above-mentioned type, while a CPU
22
in a slave system (hereinafter referred to as a “slave CPU
22
”) is being reset, a CPU
21
in a master system (hereinafter referred to as a “master CPU
21
”) writes a boot-up program for the slave CPU
22
in a dual-port memory
23
, and when the slave CPU
22
is free from its reset condition, it executes the boot-up program to boot. It is thereby possible for the slave system to have no read-only memory (ROM). The slave CPU
22
executes the boot-up program to repeatedly read and store data written in the dual-port memory
23
by the master CPU
21
, in a random-access memory (RAM)
27
. This enables transfer of data having a size greater than the capacity of the dual-port memory
23
.
In the case where the multiple-processor system Z
0
is used for an apparatus for reproducing compressed digital music data, a decoding program is stored in the RAM
27
of the slave system. In the slave system, by executing the decoding program, music data sequentially transferred from the master system are decoded to be reproduced. A decoding program for an audio compression algorithm, such as the “TwinVQ”, includes a main program and table data attached thereto. In many cases, the main program and the table data are not stored in consecutive storage areas. The table data may be partially changed depending on, for example, a piece of included music. Accordingly, before reproducing each piece of music, it is most efficient to change a portion of the table data for the piece of music. The multiple-processor system Z
0
, which is conventional, employs a method in which when program transfer from the master system to the slave system is performed, a program to be transferred is divided into portions each having a size equal to or less than the capacity of the dual-port memory
23
so that sequential transfer of the portions from the beginning is simply performed. Thus, the overall program needs to be changed, even if the program is partially changed. This takes time and leads to a waste of electric power.
According to the multiple-processor system Z
0
, when data are transferred from the master system to the slave system, the master system transfers the data by using predetermined transfer addresses and data lengths. Thus, if the specifications of the slave system are modified, those of the master system must be modified, which cannot be easily performed.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a multiple-processor system in which when data are transferred from a master system to a slave system, partial data (program) in the slave system can be only modified, whereby the master system can be flexibly adapted for modification in the specifications of the slave system.
To this end, according to the present invention, the foregoing object has been achieved through provision of a multiple-processor system comprising: a master system including a central processing unit; at least one slave system including a central processing unit and a memory writable and readable thereby; and a shared memory accessed by both the central processing unit included in the master system and the central processing unit included in the slave system; the shared memory being used to perform data transfer from the master system to the slave system in units of transfer blocks each having a size not more than the capacity of the shared memory; wherein each transfer block includes a data to be transferred from the master system or a plurality of divisional data obtained by dividing the data to be transferred; information representing a writing-start address at which the data or the plurality of divisional data starts to be written in storage for the slave system; and information representing the length of the data or the plurality of divisional data.
Preferably, the data to be transferred is a predetermined program operating in the slave system and/or data to be processed by the predetermined program.
The predetermined program may be a decoding program, and the data to be processed may be compressed digital data obtained by encoding for compression.
The data to be processed may be audio data.
The slave system and the shared memory may be integrated into a single-chip large-scale integrated circuit.
According to a multiple-processor system of the present invention, when data to be processed are transferred, a slave system notifies a master system of the start address and length of each transfer block, whereby the master system is only required to form and send each transfer block as instructed by the slave system. Therefore, if the specifications of the slave system are modified, those of the master system do not need to be modified, and can be flexibly adapted for specification modification in the slave system.
According to a multiple-processor system of the present invention, when data transfer from a master system to a slave system, a start address and a data length are added to each transfer block having a size equal to or less than the capacity of a shared memory. Therefore, by way of example, when only part of a program in the slave-system storage is changed, only the part can be easily changed by transferring data on the part to be changed to a predetermined address. Thus, compared with a case in which the entire program is retransferred, a transfer period can be shortened and the power consumption can be reduced.
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patent: 5412803 (1995-05-01), Bartow et al.
patent: 5655082 (1997-08-01), Umekita et al.
patent: 5951683 (1999-09-01), Yuuki et al.
patent: 5987506 (1999-11-01), Carter et al.
patent: 6018782 (2000-01-01), Hartmann
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Separate-vol. of I/O, Research on use of FM-8, pp. 60-64, 250-251, 267.
Harada Kazushige
Shimoda Toshiaki
Takahashi Tetsuya
Yamashita Toshiro
Chang Jung-won
Kabushiki Kaisha Kobe Seiko Sho
Maung Zarni
Reed Smith LLP
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