Multiple processor synchronized halt test arrangement

Details Multiple processor synchronized halt test arrangement Multiple processor synchronized halt test arrangement

1982-11-17

1985-02-26

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

045021163

ABSTRACT:
A hardware and algorithm synchronizing arrangement comprising a subsystem synchronization interface circuit is disclosed for controlling the testing of multiple interconnected processors. The circuit permits the pausing of one processor to cause the other interconnected processors to pause as well. The circuit enables a synchronized resumption of the interconnected processors operations. Logic circuitry and signaling interconnections control individual and multiple simultaneous pauses and full duplex operation of a plurality of central control facilities.

REFERENCES:
patent: 4128876 (1978-12-01), Ames et al.

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