Multiple processor, distributed memory computer with out-of-orde

Details Multiple processor, distributed memory computer with out-of-orde Multiple processor, distributed memory computer with out-of-orde

1997-06-27

1999-08-24

Donaghue, Larry D.

3958003, 39580011, G06F 1500

Patent

active

059435011

ABSTRACT:
A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.

REFERENCES:
Kaxiras, Kiloprocessor Extension to SCI, Apr. 1996.
Kaxiras et al. The Glow Cache Coherence Protocol Extension for Widely Shared Data, May 1996.
Burger et al. Memory Band Width Limitations of Future Microprocessors, May 1996.
Burger System Level Implication of Processor-Memory Integration, Jun. 1997.
Burger et al. Data Scalar Architecture and SPSD Execution Model, Jun. 1997.

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