Multiple processor data processing system with processors of var

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364228, 3642281, 364229, 3642291, 364230, 3642303, 364231, 3642327, 364238, 364239, 3642393, 364280, 3642801, 3642802, 3642803, 3642804, 364DIG1, 364DIG2, G06G 124, G06G 945

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051013428

ABSTRACT:
This data processing system has different kinds of microprocessors, a memory bus, a memory which is connected to the microprocessors through the memory bus, and a control circuit to selectively activate one of the microprocessors. A feature of the control circuit of this data processing system is that it has a selection controller in which a selection data item is set by the active one of the microprocessors and a selector for supplying rest mode signals to the microprocessors, excluding the one microprocessor corresponding to the content of the selection controller.

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patent: 4947478 (1990-08-01), Maeno
Microcomputer Hardware Handbook, 1st ed. Pomona, Calif., Elcomp Publishing, Inc., 1982, pp. 315, 319, 320, 389, 390, 471, 473.

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