Boots – shoes – and leggings
Patent
1982-08-10
1985-08-06
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 700
Patent
active
045339937
ABSTRACT:
The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency.
Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers.
Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.
REFERENCES:
patent: 3979728 (1976-09-01), Reddaway
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4174514 (1979-11-01), Sternberg
patent: 4215401 (1980-07-01), Holsztynski et al.
patent: 4251861 (1981-02-01), Mago
patent: 4270169 (1981-05-01), Hunt et al.
patent: 4270170 (1981-05-01), Reddaway
patent: 4384273 (1983-05-01), Ackland et al.
patent: 4412303 (1983-10-01), Barnes et al.
The Radio and Electronic Engineer, vol. 45, No. 3, Mar. 1975, pp. 116-120, London, GB; P. M. Thompson et al.: "Digital Arithmetic Units for a High Data Rate".
IEEE Transactions on Computers, vol. C-24, No. 3, Mar. 1975, pp. 317-322, New York, US; J. Deverell: "Pipeline Iterative Arithmetic Arrays".
Electronics Letters, vol. 8, No. 4, 24th Feb. 1972, pp. 100-101, Hitchin, Herts, GB; K. J. Dean et al.: "General Iterative Array".
Signal Processing: Theories and Applications, Proceedings of Eusipco-80, First European Signal Processing Conference, 16th-18th Sep. 1980, Lausanne, CH, North-Holland Publishing Company, Amsterdam, NL; L. Ciminiera et al.: "High Speed Correlator Circuits".
IEEE Transactions on Computers, vol. 21, No. 8, Aug. 1972, pp. 880-886, IEEE, New York, US; T. G. Hallin et al.: "Pipelining of Arithmetic Functions".
Automatisme, vol. 21, No. 10, Oct. 1976, pp. 302-314, Paris, FR; M. Mrayati et al.: "Conception et Realisation de Filtres Numberiques".
Electronics Letters, vol. 18, No. 6, Mar. 1982, pp. 241-243, London, GB; J. V. McCanny et al.: "Implementation of Signal Processing Functions Using 1-Bit Systolic Arrays".
Computer, Jan. 1980 (IEEE), pp. 26-40, Foster, M. J. and Kung, M. T.
Systolic Arrays (for VLSI), Kung and Leiserson, in "Introduction to VLSI Systems" by Mead & Conway, Addison-Wesley (1980).
"Matrix Triangularization by Systolic Arrays", Proc. Spie, vol. 28, Real Time Signal Processing IV (1981) Kung and Gentleman.
IEEE Transactions on Communications, Apr. 1976, pp. 418-425, Lyon, R. F.
McCanny John V.
McWhirter John G.
Lee Jameson
National Research Development Corp.
Shaw Gareth D.
LandOfFree
Multiple processing cell digital data processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple processing cell digital data processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple processing cell digital data processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-516199