Multiple power supply circuit architecture

Details Multiple power supply circuit architecture Multiple power supply circuit architecture

1999-01-13

2002-04-02

Nguyen, Matthew (Department: 2838)

Electricity: power supply or regulation systems

In shunt with source or load

Using a three or more terminal semiconductive device

Reexamination Certificate

active

06366061

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to a multiple power supply circuit architecture and, more particularly, to a method and apparatus for significantly reducing power consumption during sleep-mode without reducing circuit speed.
2. Description of the Background
Many modern integrated circuit systems shut down certain circuit blocks when their capabilities are not needed, in order to save power; e.g., sleep mode in a lap top computer. For simple static CMOS logic, sleep mode can be implemented by gating the clock that drives the latches at the input to the logic functions. For static CMOS logic, if the inputs do not change value, then only static leakage power is dissipated. Normally, static logic circuits dissipate 3 to 6 orders of magnitude less power during sleep mode, so power dissipation during sleep mode is minimal.
However, it is known to design a circuit with a two power supply system. See, for example, U.S. Pat. No. 5,814,845, issued to Carley. Such a system can reduce power consumption and maintain circuit speed. In such a circuit, however, the static leakage power is a significant fraction of the total power. That is because multiple power supply circuits sometimes cause “underdriving” of the input of static CMOS logic gates, which results in a higher leakage current, just as lowering the V
T
does. In general, for systems which employ CMOS logic gates without any form of preamplifiers, the voltage of the smaller power supply is adjusted such that during normal operation the power dissipated by switching (both capacitive charging power and short-circuit power) is approximately equal to the power dissipated by static leakage currents.
Some circuits have tried to address increased sleep-mode power dissipation with multiple V
T
MOS devices, but they require additional masks, additional space, and result in large time delays when transitioning between “sleep” mode and normal operating mode.
Therefore, the need exists for a multiple power supply architecture that reduces leakage current and delays, particularly when transitioning between normal operating mode and “sleep” mode.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a multiple power supply circuit architecture. For example, the present invention may be embodied as a circuit power system including a first voltage rail, a first reference rail, a second voltage rail, a second reference rail, and a first selective connector between the first and second voltage rails.
The present invention may also be embodied as a circuit, including a first circuit, a first voltage rail connected to the first circuit, a first reference rail connected to the first circuit, a second circuit, a second voltage rail connected to the second circuit, a second reference rail connected to the second circuit, and a first selective connector between the first and second voltage rails.
The present invention also includes a method of controlling a power system for a circuit, including providing a first power supply, providing a second power supply, connecting the first power supply to the second power supply for sleep mode, and disconnecting the first power supply from the second power supply for non-sleep mode.
The present invention solves problems experienced with the prior art because by providing a circuit with reduced sleep-mode power consumption without reduced circuit speed. Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow.


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