Multiple power source memory control circuit for memory devices

Details Multiple power source memory control circuit for memory devices Multiple power source memory control circuit for memory devices

1993-05-27

1996-02-06

Popek, Joseph A.

Static information storage and retrieval

Powering

Data preservation

365227, 365226, 36523003, 365 52, G11C 514

Patent

active

054901189

ABSTRACT:
A memory control circuit for controlling a memory chip enable signal without unnecessary power consumption in a non-volatile memory chip during the backup state. When a backup signal (BUP) shows that the card is in a backup state, all of the memory chip enable signal output lines are set to a high-impedance state by controlling a backup time control means inserted therein, and pull-up resistors 20 are connected to the memory chip enable signal output lines 8 connected to the volatile memory chip 2 for setting them to a "H" level, and an A power source 5 without backup is connected to the memory chip enable signal output lines 8 connected to the non-volatile memory chip 3 through a pull-up resistor 30, thereby preventing unnecessary current from flowing.

REFERENCES:
patent: 4388706 (1983-06-01), Butler
patent: 4587640 (1986-05-01), Saitoh
patent: 5016223 (1991-05-01), Kimura et al.
patent: 5212664 (1993-05-01), Shinohara
patent: 5309396 (1994-05-01), Kimura
"Interfacing considerations for Mitsubishi memory cards"; 2407 Microprocessors and Microsystems; 14(1990) Sep., No. 7, pp. 479-482, London, GB.

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