Multiple port integrated DMA and interrupt controller and arbitr

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G06F 1332

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active

047165235

ABSTRACT:
Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.

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patent: 4034349 (1977-07-01), Monaco et al.
patent: 4067059 (1978-01-01), Drechar
patent: 4215400 (1980-07-01), Denko
patent: 4417304 (1983-11-01), Dinwiddie, Jr.
patent: 4458313 (1984-07-01), Suzuki et al.
patent: 4615019 (1986-09-01), Bonci
"82258 Advanced DMA Controller Architectural Overview," Intel Corporation, 1984.

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