Multiple PLL oscillator and multiple CW radar used therefore

Details Multiple PLL oscillator and multiple CW radar used therefore Multiple PLL oscillator and multiple CW radar used therefore

2002-08-19

2004-06-08

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C375S308000, C455S112000

Reexamination Certificate

active

06747488

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiple PLL oscillator and, more particularly, to a multiple PLL oscillator suitable as an oscillator requiring both a higher transmitting frequency and reduction of phase noise in a radar performing a scan in a multiple millimeter CW radar.
2. Description of the Related Art
The principle configuration of a PLL oscillator is, as shown in
FIG. 11
, that the phase of a signal of a reference frequency fr and the phase of an output signal of a frequency divider
4
as a loop feedback signal are compared with each other by a phase comparator
1
, the result is integrated and converted to a voltage signal by a low pass filter
2
, and a voltage controlled oscillator
3
is controlled by the voltage signal. A part of an output of the voltage controlled oscillator
3
is divided by the frequency divider
4
to 1/N, the resultant is supplied as a signal to be compared to the phase comparator
1
. The frequency-divided output frequency is compared with the reference frequency fr, thereby obtaining a PLL oscillator output of a desired frequency fout (=fr×N). A multiple PLL oscillator obtaining a number of oscillation frequency outputs by changing the dividing number N of frequency is constructed.
From viewpoints of making the device simpler, making the band of an operation frequency wider, shortening time required for an oscillation frequency of a PLL circuit to reach a desired frequency (lock-up time), and the like in the actual configuration of a PLL oscillator, various PLL oscillators have been proposed.
Particularly, as a PLL oscillator adapted for use in telephones such as a mobile telephone and a portable telephone, a radio receiver, and a transceiver, having a relatively simple circuit configuration, realizing an oscillation output which is a high frequency, simultaneously, capable of varying an output frequency with short lock-up time and narrow frequency interval (frequency step), a PLL circuit as shown in
FIG. 12
has been proposed (Japanese Unexamined Patent Application No. Hei-9-64734).
In the PLL circuit shown in
FIG. 12
, an oscillation output (oscillation frequency f
1
) of a first variable frequency oscillating circuit
16
and an oscillation output of a second variable frequency oscillating circuit
24
having an oscillation frequency f
2
lower than that of the variable frequency oscillating circuit
16
are mixed by a mixer
59
. A signal indicative of a sum of the oscillation frequencies of the variable frequency oscillating circuits
16
and
24
and a signal indicative of a difference between the oscillation frequencies are supplied as an oscillation output signal of the PLL circuit and an input signal of a feedback loop via filters
57
and
58
. The feedback loop has a frequency divider
19
for dividing an oscillation signal of the frequency the difference. The phase of an output signal of the frequency divider
19
is compared with that of the signal of the reference frequency fr by a phase comparator
14
. An output of the phase comparator
14
controls the oscillation frequencies of the variable frequency oscillating circuits
16
and
24
via a low pass filter
18
.
The oscillation frequency of each of the variable frequency oscillating circuits
16
and
24
can be about the half of an output oscillation frequency fn of the PLL circuit, and the dividing number of the frequency divider can be reduced by feeding back an oscillation frequency difference fd between the variable frequency oscillating circuits
16
and
24
to the frequency divider
19
and mixing down a feedback signal of the loop to a lower frequency. Consequently, the lock-up time can be shortened and, simultaneously, the oscillation output can be changed at low frequency intervals also in a high frequency band.
In the PLL oscillating circuit shown in
FIG. 12
, a problem which occurs in a use where the circuit operates at the frequency interval of tens to hundreds kHz of the oscillation frequency in the millimeter wave band is not considered. For example, in a two frequency CW radar using millimeter waves which operates in a millimeter wave band, the frequency is switched at predetermined time intervals, and a distance and relative speed to an obstacle are detected on the basis of a Doppler shift and a phase difference of two received waves. Consequently, a reflected wave observed during a period in which an output frequency of a multiple PLL circuit is unstable due to increase in the lock-up time is handled as an indeterminate signal. The S/N ratio (=the signal of the radar−noise level) deteriorates by an amount corresponding to decrease in the total energy of the reflected wave. The more the frequency step is narrowed, the more the lock-up time increases, so that the two frequency CW radar using millimeter waves does not function at worst. In the case where the time of switching the frequency is increased so as to sufficiently observe the reflected wave, the frequency upper limit at the time of FFT (Fourier transform) in an A/D sampling period is suppressed, and an obstacle which moves at high speed cannot be detected.
In the proposed PLL circuit, the reference frequency is equal to or proportional to the frequency interval (frequency step) of the oscillation output. Therefore, the narrower the frequency interval is set, the narrower the loop band of the PLL becomes, so that the lock-up time to reach the desired frequency increases. In the case where a step frequency is hundreds kHz, the loop band of the PLL circuit is a faction of the frequency step so that the reference frequency component does not directly propagate to a voltage controlled oscillator, and lock-up time inversely proportional to the loop band is about tens &mgr;sec.
In the PLL circuit shown in
FIG. 12
, the voltage controlled oscillating circuits
16
and
24
are disposed in parallel in a single PLL loop, and the oscillation frequency difference between the oscillating circuits computed by the mixer
59
is supplied as a loop feedback signal of the PLL circuit to the frequency divider
19
. By increase in a loop gain K by reduction in the dividing number of frequency and shortened logic delay time of the frequency divider, the lock-up time is shortened.
Particularly, the PLL circuit is constructed by using the single reference frequency fr, and the output oscillation frequency fn of the PLL oscillating circuit is determined only by the reference frequency fr and the dividing number N of frequency of the frequency divider. Therefore, in the case of using the PLL circuit for a two waves millimeter wave radar of a millimeter wave band oscillation frequency and a step frequency of hundreds kHz, the dividing number of frequency becomes an enormous figure, so that it is impossible to main stability of the PLL circuit and shorten the lock-up time.
Since flicker caused by heat and external factors in the oscillating circuits
16
and
24
is absorbed as oscillation frequency variations in the PLL loop, an oscillation output in which the flicker is added and multiplied is observed. When two voltage controlled oscillators are constructed in the PLL loop, it is estimated that the state is similar to a state where a single feedback system has a plurality of oscillators, an oscillation like a double pendulum movement occurs, and the lock-up time becomes longer than lock-up time calculated from a loop band and a loop gain.
Further, since ratios of change of the oscillation frequencies f
1
and f
2
with respect to a control voltage Vc of the two voltage controlled oscillating circuits
16
and
24
are different from each other, to realize the PLL oscillating circuit, the ratios of change of the voltage controlled oscillating circuits
16
and
24
with respect to the control voltage Vc have to be constant and the frequency difference has to increase monotonously. Since the PLL loop performs a feedback control only on the frequency difference, even when the PLL operation is normally performed in the PLL loop, the freq

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