Multiple pipeline memory controller for servicing real time...

Details Multiple pipeline memory controller for servicing real time... Multiple pipeline memory controller for servicing real time...

1997-06-30

2001-02-06

Bayerl, Raymond J. (Department: 2773)

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

C345S506000, C711S151000, C711S158000

Reexamination Certificate

active

06184906

ABSTRACT:

The invention relates generally to memory controllers for servicing real time data and more particularly to memory controllers for use in video graphic control cards or telecommunication units that require real time data capture and processing.
BACKGROUND OF THE INVENTION
Video graphics controllers (VGC's) are continually being required to manage and control more complex and additional information for display on computer screens. The type of additional bandwidth of information can significantly reduce image resolution due to the inability of the VGC to obtain and route the information in a high speed and efficient manner. The problem is compounded when computers, in some cases, are also required to service both computer graphics information and television signaling information, such as in the case when the computer is required to display video signals.
Real time video information such as video signals from a cable television (CATV) broadcaster must be captured in real time or the information is lost. When a live television show is being sent to the computer, the VGC must capture and display the video in real time while also displaying overlaid graphics and servicing other requests from the central processing unit relating to other graphic display requirements such as the displaying of text. VGC's typically generate real time signal requests to store the incoming real time video image and data information in frame buffer memory such as
Also, the display screen must be refreshed constantly to avoid flickering and other problems that limit resolution. Since the frame buffer memories are accessed through the same memory interface, a read/write request for graphics information competes with a read/write request for capturing the real time video information. When these requests occur at the same time, one of the real time requests must wait to be serviced. This can result in a loss of data or an unacceptable slow down in processing.
These problems become compounded where the display screens are higher resolution displays and when other graphic information such as graphical user interfaces and other graphics are overlaid with the video image information and the information is requested to be displayed at the same time. The more the VGC has to switch between the real time requests, the lower the resolution quality and the lower the system performance.
To help alleviate some of these problems, memory controllers in VGC's have employed a single multi-stage pipeline processing approach. Such memory controllers achieve relatively high speeds and allow for a single memory clock cycle read/write operation. However, these memory controllers typically have memory access latencies that can dramatically degrade the performance of real time requesters in the VGC's. Extrinsic memory access latencies in such VGC's can be a large number greater than 10 clock cycles and can be 21 clock cycles. With the increasing real time requirements and additional non-real time requirements, these memory controllers with a great number of memory access latencies can not offer the high speed and high performance control necessary to adequately accommodate the increasing real time processing demands and complexity.
Consequently, there exists a need for a memory controller for servicing real time data that can more effectively accommodate multiple real time memory requests. It would also be advantageous to have an integrated VGC chip that includes a memory controller that has improved memory access latency for handling both real time video capture requests and real time display requests while also effectively accommodating non-real time requests. It would also be advantageous if the memory controller allowed for use of the same size CRT controller FIFO to help reduce costs of the VGC.


REFERENCES:
patent: 5649206 (1997-07-01), Allen
patent: 5752010 (1998-05-01), Herbert
patent: 5822758 (1998-10-01), Loper et al.

Affiliated with

Also associated with

Rating

Multiple pipeline memory controller for servicing real time... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple pipeline memory controller for servicing real time..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple pipeline memory controller for servicing real time... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2559042