Multiple phase synchronous race delay clock distribution circuit

Details Multiple phase synchronous race delay clock distribution circuit Multiple phase synchronous race delay clock distribution circuit

1998-03-05

1999-12-07

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327295, 327161, 327258, 327261, H03K 514, H03L 700

Patent

active

059990325

ABSTRACT:
A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock. The delay control means will create a first phase control pulse and a second phase control pulse. A duty cycle synchronizer means is connected to the delay control means to create the dual phases of the internal clock from the first phase control pulse and the second phase control pulse. An internal buffer will buffer and amplify the two phases of the internal clock signal that is aligned with the external clock signal to have minimum skew.

REFERENCES:
patent: 5313501 (1994-05-01), Thacker
patent: 5489864 (1996-02-01), Ashuri
patent: 5663767 (1997-09-01), Rumreich et al.
patent: 5901190 (1999-05-01), Lee
T. Saeki et al. "A 2.5ns Clock Access 250Mhz, 256Mb SDRAM with Synchronous Mirror Delay", IEEE Journal of Solid State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1664.
T. Yamad et al. "Capacitive Coupled Bus with Negative Delay Circuit for High Speed and Low Power (10GB)s<500mw) Synchronous DRAM)" Digest of Papers for IEEE Symposium on VLSI Circuits, 1996, pp. 112-113.

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