Excavating
Patent
1986-10-07
1987-10-13
Miller, Stanley D.
Excavating
307269, 307480, 328109, G06F 1110
Patent
active
047003502
ABSTRACT:
A multiple phase CRC (cyclic redundancy check) generator having a clock phasing circuit having an input connected to the CRC clock source and a plurality of N phase clock outputs, and a plurality of N CRC circuits each having a data input, and a phase clock input each connected to one of the clock phasing circuit phase clock outputs, and each having a cyclic redundancy check output. The clock phasing circuit preferably is formed of a sequence of divided-by-two circuits each having an input and two outputs; there being N-1 divider circuits arranged in log.sub.2 N tiers, the divider circuits of the first tier having its input connected to the clock output and the outputs of the last tier of divider circuits each being connected to separate clock inputs of the CRC circuits.
REFERENCES:
patent: 4105999 (1978-08-01), Nakamura
patent: 4316284 (1982-02-01), Howson
patent: 4316285 (1982-02-01), Bobilin et al.
patent: 4454600 (1984-06-01), LeGresley
patent: 4593393 (1986-06-01), Mead et al.
"32-Bit CRC (Cyclical Redundancy Checking) Error Detection", Copyright 1978, Monolithic Memories Programmable Logic Handbook, Fourth Edition.
Douglas Phillip N.
Johnson Alan G.
Miller Stanley D.
Roseen Richard
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