Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1989-01-19
1990-07-17
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307243, 307468, 364716, H03K 19177
Patent
active
049423193
ABSTRACT:
A PLA is organized into a plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages for operation at any given time. Means are provided for switching pages when necessary in response to input signals including, if desired, signals fed back from the output leads of the PLA, or internal leads within the PLA. By having only a selected one or more of the pages of the PLA operable at any given time, the number of product and sum terms functioning at any given time is significantly less than the total number of product and sum terms available in the device, thereby minimizing power consumption. Furthermore, by utilizing a paged architecture, speed is increased and power consumption reduced since the number of leads connected to, and thus the capacitance of, the product and/or sum term lines is reduced.
REFERENCES:
patent: 3593317 (1971-07-01), Fleisher et al.
patent: 3849638 (1974-11-01), Greer
patent: 4034356 (1977-07-01), Howley et al.
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4233667 (1980-11-01), Devine et al.
patent: 4293783 (1981-10-01), Patil
patent: 4415818 (1983-11-01), Ogawa et al.
patent: 4422072 (1983-12-01), Cavlan
patent: 4495590 (1985-01-01), Mitchell
patent: 4506173 (1985-03-01), Yum
patent: 4506341 (1985-03-01), Kalter et al.
patent: 4583193 (1986-04-01), Kraft et al.
patent: 4617649 (1986-10-01), Kyomasu et al.
patent: 4660171 (1987-04-01), Moore et al.
patent: 4675556 (1987-06-01), Bazes
patent: 4677318 (1987-06-01), Veenstra
patent: 4703206 (1987-10-01), Cavlan
patent: 4742252 (1988-05-01), Agrawal
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4758993 (1988-07-01), Takemae
patent: 4763020 (1988-08-01), Takata et al.
patent: 4763302 (1988-08-01), Yamada
patent: 4802135 (1989-01-01), Shinoda et al.
patent: 4812678 (1989-03-01), Abe
L. D. Whitley, IBM Technical Disclosure Bulletin (1981), vol. 24, No. 6, "PLA Having OR-Array Bit Partitioning".
S. B. Greenspan, IBM Technical Disclosure Bulletin (1976), vol. 19, No. 5, "Multiple Partitioned Programmable Logic Array".
Luich Thomas M.
Pickett Scott K.
Swift, IV Arthur L.
Caserza Steven F.
Miller Stanley D.
National Semiconductor Corp.
Patch Lee
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