Multiple output synchronous rectifier circuit providing zero...

Details Multiple output synchronous rectifier circuit providing zero... Multiple output synchronous rectifier circuit providing zero...

1999-12-10

2001-10-02

Wong, Peter S. (Department: 2838)

Electric power conversion systems

Current conversion

Including d.c.-a.c.-d.c. converter

C363S089000, C363S127000

Reexamination Certificate

active

06297970

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a multiple output circuit that achieves high efficiency by using synchronous rectification and magnetic amplifiers.
BACKGROUND OF THE INVENTION
Many of the voltage regulator modules (VRMs) used for high current application use synchronous rectification.
FIG. 1
a
shows a typical non-isolated DC—DC converter VRM synchronous rectification circuit. The circuit includes first and second capacitors
12
,
20
, first and second transistors
14
,
16
an inductor
18
and a pulse width modulator
20
. In this type of configuration the first transistor
14
is referred to as the high switch and the second transistor
16
is referred to as the low switch. However, even though a synchronous mode of operation improves the efficiency of the DC—DC converter, it does not achieve an ideal Zero Volt Switch (ZVS) mode operation.
To better understand the operation of a typical synchronous rectification, refer to the wave form in
FIG. 1
b
. VG
1
illustrates the driving wave form of the first transistor
14
and VG
2
shows the driving wave form of the second transistor
16
. IQ
1
is the transistor current of the first transistor
14
and IQ
2
is the transistor current of the second transistor
16
. Vds
1
represents the drain to source voltage across the first transistor
14
and Vds
2
represents the drain to source voltage across the second transistor
16
.
Still referring to
FIG. 1
b
, when the first transistor
14
is turned on at t
0
, the voltage across it, Vds
1
, is approximately equal to V
in
. Also, during the subsequent turn off of the first transistor
14
at t
2
, it experiences the full input voltage, Vin, while current is still flowing through it. Therefore, the first transistor
14
, unlike the second transistor
16
,does not turn on at a time when there is no voltage across it. Hence, it does not operate in ZVS mode. This creates switching losses which lowers the efficiency of the circuit.
This efficiency problem is typically addressed by utilizing an isolated synchronous rectification circuit.
FIG. 2
a
is a schematic of an isolated synchronous rectifier
30
. It includes a first capacitor
31
coupled to a first high frequency transformer
32
, a winding
33
coupled to the transformer
32
, a first transistor
34
coupled to the winding
33
, a second transistor
36
coupled to the first transistor
34
, an inductor
38
coupled to the second transistor
36
a capacitor
40
coupled to the inductor
38
, a third transistor
42
, a second transformer
44
and a pulse width modulator
46
. By incorporating the transformer
32
, an ideal Zero Volt Switch (ZVS) operation is achieved in both transistors
34
,
36
, wherein if the first transistor
34
is on, the second transistor
36
is off and only its body diode will be conducting.
Please refer now to
FIG. 2
b
. VG
1
illustrates the driving wave form of the first transistor
34
and VG
2
shows the driving wave form of the second transistor
36
. IQ
1
is the transistor current of the first transistor
34
and IQ
2
is the transistor current of the second transistor
36
. Vds
1
represents the drain to source voltage across the first transistor
34
and Vds
2
represents the drain to source voltage across the second transistor
36
. Unlike the non-isolated synchronous rectifier, when the first transistor
34
is turned on at t
0
, Vds
1
is approximately zero volt. Furthermore, when the second transistor
36
is turned on at t
2
, Vds
2
is approximately at zero volt. Accordingly, both the first transistor
34
and the second transistor
36
operate in ZVS mode.
This solution improves efficiency, but it is only beneficial in the operation of a single output synchronous rectifier where a single output voltage is desired. Ergo, this solution would not work in a multiple output circuit where several different output voltages are provided based upon one input voltage and a single isolate transformer. For example, a typical computer power supply system may require output voltages of +3.3V, +5V, +12V, etc. Consequently, in applications where different output voltages are generated from a single input voltage, the isolated synchronous rectifier circuit of
FIG. 2
is not an effective solution. Accordingly, what is needed is an improved multiple output synchronous rectification circuit. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A zero voltage switching synchronous rectification circuit for providing multiple output voltages from a single input voltage is disclosed. The circuit comprises a single transformer coupled to the single input voltage and at least two synchronous rectifiers, each of the at least two synchronous rectifiers being coupled to the transformer via a winding, each of the at least two synchronous rectifiers including a first controlled switching device coupled to the winding, wherein at least one of the at least two synchronous rectifiers includes a delay element, wherein the first controlled switching device of the at least one of the at least two synchronous rectifiers is coupled to the winding via the delay element, wherein the delay element delays the input voltage across the at least one of the at least two synchronous rectifiers for a predetermined amount of time.
By incorporating a delay element with a plurality of isolated synchronous rectifiers, Zero Voltage Switching is achieved in a multiple output environment. This will improve the efficiency of multiple output circuits because the transistors will not incur the switching losses that are present in the operation of conventional synchronous rectification circuitry where a DC voltage is generated prior to generating a lower voltage output through synchronous rectification.


REFERENCES:
patent: 5612862 (1997-03-01), Marusik et al.
patent: 5991171 (1999-11-01), Cheng
patent: 6038150 (2000-03-01), Yee et al.

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