Multiple output phase-locked loop (PLL) using a single...

Details Multiple output phase-locked loop (PLL) using a single... Multiple output phase-locked loop (PLL) using a single...

2007-04-24

2007-04-24

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C331S011000

Reexamination Certificate

active

11115023

ABSTRACT:
Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment, the base module generates signals with a controlled frequency, multiple equidistant phase, and reduced duty cycles. Frequency dividers using barrel-shifters driven by an early-late detector combined with a left/right “one hot” shift-register or driven by an early-late detector combined with up-down counter/decoder are also disclosed.

REFERENCES:
patent: 5059924 (1991-10-01), JenningsCheck
patent: 5063937 (1991-11-01), Ezenwa et al.
patent: 5548251 (1996-08-01), Chou et al.
patent: 6351165 (2002-02-01), Gregorian et al.
patent: 2001/0006356 (2001-07-01), Norskov et al.
patent: 2003/0214335 (2003-11-01), Saeki

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