Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Using particular code or particular counting sequence
Reexamination Certificate
2002-04-15
2004-03-16
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Using particular code or particular counting sequence
C377S034000, C377S035000, C377S036000, C377S056000
Reexamination Certificate
active
06707874
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT Not applicable
REFERENCE TO A MICROFICHE APPENDIX
Not applicable
BACKGROUND
1. Field of Invention
The invention relates to digital counting in different number systems, particularly for analog-to-digital and for digital-to-analog converters with circuitry shared among multiple parallel conversion operations or among differing conversion structures.
2. Description of Prior Art
Digital counters are ubiquitous in both digital and mixed-signal electronics. For example, digital counters are used to track elapsed time in analog-to-digital (A/D) converters in which a comparator indicates when a time-varying difference between an unknown input signal and a deterministic reference signal reaches zero. Similarly, a digital counter may be used in a digital-to-analog (D/A) converter, such as those of the US PTO application SHARED PARALLEL DIGITAL-TO-ANALOG CONVERSION. In that application, multiple digital numbers to be converted to analog signals are compared to a shared running count. When each digital number matches the count, a reference analog signal is sampled and held.
Prior art A/D converters and D/A converters which use counters often use counting systems such as signed magnitude or offset binary. These are convenient because it is easy to make suitable counters with these systems, and also because there is a natural connection between these systems and the base-2 logarithmic decompositions (in the case of A/D conversion) or compositions (in the case of D/A conversion) of analog signals. However, much digital calculation uses two's complement number systems, which offer easy arithmetic operations including addition, subtraction, negation, and multiplication.
In a typical A/D converter, one counter is used for one conversion operation. The counter is reset when a second conversion is carried out. Usually, the technique or structure of the first conversion operation is identical to the technique or structure of the second conversion operation, with a waveform and a corresponding count sequence that are the same. However, there are a few prior art examples of parallel AID converters in which a counter is used simultaneously for multiple conversions. In these examples, the non-shared circuitry for the various conversion operations is usually identical, and the shared circuitry serves an identical purpose in each of the parallel conversions.
A disadvantage of existing techniques for A/D and D/A conversion are that number systems which are well-suited to converter architectures may not be the same number systems that are used for other digital computation. It may be necessary to include extra circuitry or programming instructions devoted to translating between the number formats. Moreover, in A/D and D/A converters where counters are shared elements of parallel conversion operations, non-shared circuitry is usually of identical construction, which may limit the cost savings of sharing.
SUMMARY
The present invention is a technique for using a single counting circuit to provide a variety of different count sequences, which eliminates the need for special translation circuitry between A/D or D/A converters and other digital computation circuitry and which reduces the cost of implementing parallel and shared parallel converters.
OBJECTS AND OBJECTIVES
There are several objects and objectives of the present invention.
It is an object of the present invention to provide a simple counter which can count in a desired number system such as sign-magnitude, offset binary, or two's complement.
It is another object of the present invention to provide a simple counter which can count up or down in a desired number system such as sign-magnitude, offset binary, or two's complement.
It is still another object of the present invention to provide a simple counter which can count up and down simultaneously in a desired number system such as sign-magnitude, offset binary, or two's complement.
It is a further object of the present invention to provide a simple counter which can count in multiple desired number systems such as sign-magnitude, offset binary, and two's complement.
It is another object of the present invention to provide a counter which can be used as either a shared or a non-shared component in A/D converters which may operate in parallel.
It is another object of the present invention to provide a counter which can be used as either a shared or a non-shared component in D/A converters which may be operating in parallel.
It is another object of the present invention to provide an A/D converter which can produce outputs in multiple digital number formats.
It is another object of the present invention to provide a D/A converter which can accept inputs in multiple digital number formats.
Further objects and advantages of the invention will become apparent from a consideration of the ensuing description.
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U.S. patent application Ser. No. 10/084,803, Murphy, filed Feb. 28, 2002.
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