Multiple operations employing divided arithmetic logic unit and

Details Multiple operations employing divided arithmetic logic unit and Multiple operations employing divided arithmetic logic unit and

1995-06-07

1997-01-07

Envall, Jr., Roy N.

Boots, shoes, and leggings

3647365, 364784, G06F 738, G06F 700, G06F 750

Patent

active

055924050

ABSTRACT:
A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.

REFERENCES:
patent: 4293907 (1981-10-01), Huang et al.
patent: 4761754 (1988-08-01), Kinoshita
patent: 4933878 (1990-06-01), Guttag et al.
patent: 4985848 (1991-01-01), Pfeiffer et al.
patent: 5025407 (1991-06-01), Gulley et al.

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