Multiple on-chip IDDQ monitors

Details Multiple on-chip IDDQ monitors Multiple on-chip IDDQ monitors

1996-10-16

1998-05-26

Karlsen, Ernest F.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

3241581, G01R 3128

Patent

active

057572038

ABSTRACT:
In order to measure IDDQ in a large integrated circuit, multiple IDDQ monitors sampling the current drawn by selected portions of the circuit are placed on the integrated circuit chip. The output of each IDDQ monitor is combined and supplied to one output port when any of the IDDQ monitors detect current in excess of a predetermined threshold. The output of each IDDQ monitor is also stored in a memory for subsequent readout at a second output port for detection of particular portions drawing the excessive current.

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"CMOS IC Fault Models, Physical Defect Coverage, and IDDQ Testing", by: Ronald R. Fritzemeier, Charles F. Hawkins, and Jerry M. Soden, IEEE 1991 Custom Integrated Circuits Conference, IEEE, pp. 13.1.1-13.1.8.
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