Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-10-21
2001-05-15
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S152000, C327S153000
Reexamination Certificate
active
06232806
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to signal distribution in digital circuits and systems and, more particularly, to clock signal distribution of in-phase clock signals within a large digital system with low chip-to-chip and card-to-card skew.
BACKGROUND OF THE INVENTION
In multiprocessor computer systems employing synchronous clocking schemes, it is generally necessary to distribute many copies of a low skew clock signal over long distances. Clock skew is regarded as a principal design parameter with regard to the design and implementation of high-speed, distributed clock systems. Clock skew is generally understood in the art as a difference in time between the rising edge of one clock pin relative to another clock pin. Clock skew is generated by differences in delay between the system clock oscillator and the clock pins. This delay typically results from a combination of the delay through different clock drivers and the time required for the clock signals to propagate down the PC board trace wires, often referred to as trace delay.
The clock driver chips employed in large digital systems are typically limited in terms of the number of driver outputs, thus requiring that several chips be connected in a parallel clock signal repowering configuration. It is possible, through careful designing, to minimize driver-to-driver skew on a single chip using various layout and circuit design techniques, such as optimizing wiring and device matching.
Clock driver skew with respect to a chip-to-chip configuration, however, is primarily a function of chip process variations, and generally can not be controlled adequately through good physical and circuit design practices. Further complicating the effort of designing multiple-chip clock distribution circuitry is card-to-card skew. Such card-to-card skew may be due to either process variations or technology variations.
A known approach to addressing chip-to-chip and card-to-card clock skew involves the use of one or more phase lock loop (PLL) circuits per chip. PLL's are typically employed in prior art designs to provide a requisite level of clock signal phase alignment. The use of PLL's in accordance with prior art approaches, however, generally complicates the clock distribution scheme, since PLL's typically require unique wiring blockage, layout, power distribution, and characterization. Additionally, crosstalk becomes a concern when using more than one PLL per chip.
There exists a keenly felt need for a clock distribution architecture that overcomes the above-noted deficiencies found in prior art implementations, and one that provides for low clock skew in chip-to-chip and card-to-card configurations. The present invention fulfills these and other needs.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for distributing a signal to a number of receiving devices in a synchronous manner. In accordance with one embodiment of the present invention, a number of signals each having a respective delay are produced and transmitted to one of a number of receiving devices. The delay of each of the delayed signals is adjusted using a reference signal and an output signal provided by each receiving device such that the delayed signals are received by respective receiving devices at approximately the same time.
Adjusting the delay of the delayed signals involves adjusting a phase of each of the delayed signals to a substantially in-phase relationship with respect to the reference signal in response to a phase difference between the reference signal and each of the respective output signals. The output signals are preferably data signals. The delayed signals and the output signals may respectively represent low voltage differential signals or CMOS level signals.
The reference signal is preferably a signal having a fixed delay longer in duration than the delayed signals. Producing each of the delayed signals may involve selecting between one of a first delay line or a second delay line, and producing the delayed signal using the selected first or second delay line. A delay factor of the other one of the first or second delay lines may be adjusted by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines. A reference voltage having a substantially constant amplitude with respect to the power supply may be provided to the one or more delay elements in order to minimize delay variations due to power supply voltage variations.
In another embodiment, an apparatus and method according to the present invention is implemented in a computer or digital system for distributing a clock signal within circuitry disposed on either a single system card or on a number of separate system cards. A main system card generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the main system card receive one of the variable clock signals.
A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal and output signal received from each of the separate system cards.
In one embodiment, producing each of the variable clock signals involves selecting between a first delay line or a second delay line, and then producing the variable delay signal using the selected first or second delay line. A delay factor of the non-selected first or second delay line may be changed by varying a resistance and a current of one or more delay elements of the non-selected first or second delay lines. A reference voltage having a substantially constant amplitude with respect to the power supply may be provided to the delay elements of the first and second delay lines to minimize unintended variations to delay characteristics due to power supply voltage variations.
An adaptive clock distribution circuit according to an embodiment of the present invention includes a master module comprising a fixed delay line and a number of variable delay line circuits. Each of the variable delay line circuits and the fixed delay line receive a system clock signal. The fixed delay line produces a delayed clock signal using the system clock signal. The master module is coupled to a primary slave module which receives the delayed clock signal from the fixed delay line, and produces a reference clock signal using the delayed clock signal. The primary slave module may be coupled to one or more separate logic devices.
The master module is coupled to a number of secondary slave modules, each of which is coupled to one or more separate logic devices. The secondary slave modules are provided on a respective system card separate from the system card provided for the master module. Each of the secondary slave modules receives a variable clock signal from one of the variable delay line circuits, and provides a slave output signal, such an output data signal, which is fed back to the master module.
The master module adjusts the variable clock signal of each of the secondary slave modules to be in substantial alignment with the reference clock signal in response to a phase difference between respective slave output signals and the reference clock signal. The variable clock signal received by each of the secondary slave modules is used for clocking respective separate logic devices.
The master module, in accordance with an embodiment of the present invention, includes a number of control circuits and a number of phase detectors. Each of the control circuits is coupled to one of the variable delay line circuits and one of the phase detectors. Each of the phase detectors receives the reference clock signal from the primary slave module and a slave output
Rudolph Bruce George
Strom James David
Woeste Dana Marie
Hollingsworth Mark A.
International Business Machines - Corporation
Lam Tuan T.
Mueting & Raasch
Nguyen Hiep
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