Multiple microprocessor watchdog system

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Details

371 62, G06F 1100, G06F 1128, G06F 1132/11/30

Patent

active

048112003

ABSTRACT:
A main microprocessor A (11) provides data to a display formatter microprocessor B (12) via a data bus (13). Microprocessor B provides data and latch (activity) pulses (34A) to a visual display (27) comprising a number of individual display devices (28-30) which are sequentially excited by data obtained from microprocessor B. An external activity detector (38), in response to an absence of the latch pulses of microprocessor B for a predetermined time, generates a reset signal (40) for resetting the microprocessor A. In response to being reset, microprocessor A provides an output control signal (at 20) which results in the resetting of the microprocessor B. If microprocessor B determines that microprocessor A is not properly providing data to it, microprocessor B will terminate generating the latch pulses (34A). The preceding configuration results in each of the microprocessors effectively monitoring the operation of the other microprocessor so as to insure proper system operation. Therefore, this system properly resets itself in response to any of a large number of different failures which may occur in either of the microprocessors, and this is accomplished with a minimum of additional hardware circuitry and software programming.

REFERENCES:
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patent: 4558416 (1985-12-01), Pauwels et al.
patent: 4597052 (1986-06-01), Matsuda
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patent: 4683568 (1987-07-01), Urban
patent: 4689766 (1987-08-01), Kent
patent: 4696002 (1987-09-01), Schleupen et al.
patent: 4726024 (1988-02-01), Guziak et al.

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