Multiple-microcomputer processing

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G06F 1300

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044146248

ABSTRACT:
The architecture of a special-purpose multiprocessor, hierarchically structured and functionally distributed, having ditributed cache memory for local processing and a common applictions task manager in each microcomputer. A group of identical microcomputers execute the total program in an intrinsically parallel mode within the frame times scheduled by a system state control microcomputer.

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Chen, B. Y., "Microcoding a Bit-Slice Super Minicomputer," Proceedings of e Southeastcon 1980, Apr. 1980.
Pettus, R. O., "Multiple Microcomputer Control Algorithm," Technical Report Navtraequipcen 78-C-0157-1, Sep. 1979.
Avila, J., "Memory Alignment Controller for a Bit-Slice 32-Bit Computer" Proceedings of Twelfth Annual Southern Symposium on System Theory, May 1980.

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