Chemistry: analytical and immunological testing – Process or composition for determination of physical state... – Surface area – porosity – imperfection – or alteration
Reexamination Certificate
2000-01-20
2002-09-10
Warden, Jill (Department: 1743)
Chemistry: analytical and immunological testing
Process or composition for determination of physical state...
Surface area, porosity, imperfection, or alteration
C216S038000, C216S052000, C216S083000, C216S084000, C216S085000
Reexamination Certificate
active
06448084
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit failure analysis. More particularly the invention relates to preparing highly defined cross sectional samples of the metal layers of integrated circuits for micrographic analysis.
BACKGROUND
Micrographic analysis is an important tool in many different sectors of the microelectronics industry, including research, development, production control, and failure analysis. For example, the failure mode of certain inoperable or sub optimal integrated circuits is determined by visual inspection of the device at magnitudes on the order of 5,000 times the original size of the device, by techniques such as scanning electron microscopy.
Typically, the type of photomicrograph desired falls into one of two general categories, either a top surface analysis or a cross sectional analysis. The sample to be analyzed must typically be properly prepared in order to achieve an informative image using either one of these two techniques. Cross sectional analysis tends to present additional challenges beyond those encountered with top surface analysis. Typically, sample preparation for cross section analysis receives most of the same steps desired for sample preparation for top surface analysis, plus additional steps uniquely desired for cross sectional analysis.
For example, in order to view a device sample along a cross section, it is typically necessary to create the desired cross section in some manner. This is accomplished in a variety of ways, such as fracturing, mechanically slicing, or abrading the sample. Whichever method is used, it is desired that, except for the break along the desired cross section itself, the sectioning process does not create other physical anomalies that may confound or alter the physical characteristics of the device that is under investigation. One undesired physical anomaly that tends to occur during sectioning is blurring of the metallic layers of the integrated circuit. As these metallic layers tend to be relatively ductile as compared to the other layers, there is some tendency for one or both of two different types of blurring to occur.
First, blurring of the metal within a single layer of a thin film tends to hide the physical characteristics of the metal, such as grain size. Second, blurring between the different metal layers of a multiple metal layer thin film, which layers are typically disposed one upon the other, tends to obscure the interfaces at which a layer of one metal type ends and a layer of another metal type begins.
While certain of the known techniques for physically sectioning the integrated circuit tend to produce generally better results in this regard than others of the known sectioning techniques, control of metallic layer blurring tends to be insufficiently controlled by sectioning techniques alone. Further, even when very little blurring or no blurring at all is evident, sectioning techniques alone tend to produce cross sections where very little if any resolution of grain size or distinction between the different metal layers is detected.
What is needed, therefore, is a system to both resolve the interfaces between the layers of multiple layer metal films so that the different metal layers are more readily detectable, and also to clarify the individual metal layers of those multiple layer metal films to help resolve the physical characteristics of the individual metal layers.
SUMMARY
The above and other needs are provided by a method for preparing at least one metal layer of an integrated circuit for visual analysis. The at least one metal layer to be visually analyzed is exposed, and a solution of nitric acid, acetic acid, and ammonium fluoride is applied to the at least one metal layer. The at least one metal layer is rinsed to substantially remove the solution, and the integrated circuit is dried.
In various preferred embodiments, the solution is made with one part nitric acid, three parts acetic acid, and two parts ammonium fluoride. The nitric acid is a solution of about seventy percent by weight in water, the acetic acid is glacial acetic acid, and the ammonium fluoride is a solution of about forty percent by weight in water. The solution is preferably at a temperature of about seventy degrees Fahrenheit. In a most preferred embodiment, the solution is applied to the at least one metal layer by swabbing the solution onto the layer for between about ten seconds and about fifteen seconds.
The step of exposing the at least one metal layer preferably includes sawing the integrated circuit along a desired cross section. Material is further removed from the integrated circuit by abrasion until a desired cross section is exposed. Preferentially, the exposed at least one metal layer of the integrated circuit is polished. This method is particularly useful for clarifying the physical characteristics of the metal layers, including grain size, thickness, and adhesion. In a most preferred embodiment, the exposed and clarified metal layers are visually analyzed with a scanning electron microscope.
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Batteate Patricia M.
Griley Kristine T.
Gakh Yelena
LSI Logic Corporation
Luedeka Neely & Graham PC
Warden Jill
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