Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1998-10-22
2001-07-10
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S002000, C257S016000, C257S055000, C257S063000
Reexamination Certificate
active
06259116
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices comprising silicon-rich amorphous silicon alloy memory elements which are electrically-programmable through current induced conductivity.
A semiconductor memory device of the above kind is described in PCT WO 96/19837. The memory elements in this device comprise a layer of hydrogenated, silicon rich amorphous silicon alloy material, containing at least one other element in addition to hydrogen and silicon, for example nitrogen or carbon, which material is sandwiched between a pair of electrically conductive contact layers. The memory element is programmed by inducing a defect band throughout a region of the amorphous silicon alloy layer, for example by electrical current stressing, which lowers the activation energy for the transport of carriers in the layer by a selected amount which can be varied. By tailoring this defect band, or more specifically the concentration and distribution of energies of the defects in the defect band, the extent of the lowering of the activation energy level of the element can be selectively set to programme the element. The memory element is effectively an analogue memory element as the amount of activation energy lowering can be selected from a more or less continuous range rather than just two states. The memory elements differ from other known thin film memory elements using amorphous silicon alloy material of the so-called filamentary kind in which a localised filamentary region is produced by a so-called forming process which causes, it is believed, a top metal contact to diffuse into the doped amorphous silicon layer, in that their structure and operation does not involve or depend on the presence of filaments. Rather, the induced defect band leads to the element having a bulk controlled effect which is proportional to its area. These memory elements are highly reproducible and are capable of being programmed over a comparatively wide range, for example around three orders of magnitude or more. When fabricated in an array on a common substrate using common-deposited layers, the behaviour of individual memory elements is highly predictable and similar. Aforementioned PCT WO 96/19837 describes embodiments of memory devices comprising arrays of such memory elements. The memory elements are arranged in a 2D matrix array on a substrate and addressed via crossing sets of row and column conductors, with individual memory elements being defined at the respective intersections of the row and column address conductors. The array of memory elements is fabricated by depositing a layer of conductive material over the substrate, photolithographically patterning this layer to define one set of address conductors, depositing a continuous layer of the amorphous silicon alloy material over these conductors and then depositing a further layer of conductive material over the amorphous silicon alloy layer and photolithographically patterning this layer to define the other set of address conductors. A plurality of 2D arrays of memory elements stacked upon one another is produced successively in this manner to form a multi-level memory array device with each array having sets of address conductors. A set of address conductors associated with one array may serve also as one set of address conductors for an adjacent array. In this structure, therefore, each memory element in one array is individually addressable and each array of memory elements is addressed separately. The storage capacity of the memory device is thus determined by the number of memory elements in each array and the number of arrays.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved memory device using the above-described kind of memory element.
It is another object of the present invention to provide a memory device using the above-described kind of memory elements which has a comparatively large capacity and which can be fabricated in a simple and inexpensive manner.
According to the present invention there is provided a semiconductor memory device comprising a multiplicity of memory elements each comprising hydrogenated silicon-rich, amorphous silicon alloy material between a pair of contacts which is characterised in that the device comprises a layer of said amorphous silicon alloy material, sets of input and output contacts on opposing sides of the layer, and discrete conductive elements disposed in the layer which for each input contact define programmable conductive paths between the input contact and a plurality of output contacts. With this structure a three dimensional network of memory elements is available. Pairs of conductive elements within the layer and at an appropriately small spacing can, together with the alloy material situated therebetween, constitute a memory element programmable through current induced conductivity. Similarly, a memory element can be constituted by an input, or output, contact together with a conductive element within the layer and the region of alloy material separating them. When voltages are applied to input and output contacts, electrical current paths through the layer are generated with the conductive elements acting as nodes and, together with the intervening alloy material, forming programmed memory elements through the phenomenon of current induced conductivity which uses the generation of defects in the silicon-rich amorphous silicon alloy material to form a defect band through which an electrical current can pass. The present invention thus involves a more general approach to the use of current induced conductivity by moving away from a formal 2D structure to provide a three dimensional memory network. Unlike the memory array device of PCT WO 96/19837, which consists merely of separately addressable, formal 2D arrays stacked upon one another, the memory device of the present invention has a truly 3D structure. In some respects, the memory element structure obtained resembles a neural network.
The contacts of one, or both of the sets of input and output contacts may be in the form of strips. However, the sets of input and output contacts preferably both comprise regularly spaced contacts arranged in rows and columns in order to realise the potential of the memory structure to a further extent and achieve greater storage possibilities. The input and output contacts need not be aligned overlying one another however, and may have different pitches. The nodes constituted by the conductive elements within the alloy layer define possible current paths through the body of the alloy layer and enable defects to be generated to a concentration determined by the degree of current stressing and the defect concentration then determines the conductivity in localised regions of the alloy layer. Using this capability, the memory device structure can be programmed to give many outputs for each input that is a function of more than one input. It may also be possible to change the outputs for a given input as a function of the programming of neighbouring inputs. The structure may thus be considered to behave in the manner of a neural network with the processing power being embedded in the body of the structure. One application of the memory device could be as a very large memory. If, for example, every input contact in an n by n array has n by n outputs then the memory power would be n to the power of 4.
The conductive elements constituting the nodes may for simplicity comprise conductive particles quasi-randomly dispersed throughout the thickness of the amorphous silicon alloy layer. Alternatively, the conductive particles may be dispersed quasi-randomly at one or more discrete levels in the body of the alloy layer between its opposing sides. Preferably, however, the conductive elements comprise conductive layer portions formed at one or more discrete levels in the body of the alloy layer between the opposing sides. The positions and dimensions of the conductive layer portions are preferably predetermined. In this way, the programming pos
Biren Steven R.
Fenty Jesse A.
Lee Eddie C.
U.S. Philips Corporation
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