Multiple memory bit/chip failure detection

Details Multiple memory bit/chip failure detection Multiple memory bit/chip failure detection

1995-12-15

1997-03-18

Beausoliel, Jr., Robert W.

Excavating

G06F 1100

Patent

active

056129653

ABSTRACT:
An apparatus for efficiently detecting errors in a system having a plurality of memory devices. The present invention uses a single parity bit configuration to detect common data errors caused by faulty memory devices including multiple data errors within one memory device. This is accomplished by effectively turning a multiple bit error detection situation into a single bit error detection situation. Thus, instead of allocating a contiguous block of bits to the same memory unit, the present invention allocates bits across all memory units in a round-robin fashion. The parity domains are defined such that multiple errors within one SRAM can be detected despite only using a single bit parity configuration.

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