Multiple memory bank parity checking system

Details Multiple memory bank parity checking system Multiple memory bank parity checking system

1989-11-22

1991-09-24

Beausoliel, Robert W.

Excavating

371 511, G06F 1110

Patent

active

050520016

ABSTRACT:
A ROM/PROM memory system circuit structure provides for vertical expansion of data words while providing for enablement of parity checking by the addition of a single auxiliary ROM/PROM memory chip which duplicates the type and size of data memory chips. Additionally, selection means is provided to choose either an odd parity or an even parity format.

REFERENCES:
patent: 4019033 (1977-04-01), Parmet
patent: 4271521 (1981-06-01), Mahmood
patent: 4295219 (1981-10-01), Draper
patent: 4355393 (1982-10-01), Kubo
patent: 4464755 (1984-08-01), Stewart
patent: 4800535 (1989-01-01), McAlpine
patent: 4809278 (1989-02-01), Kim
patent: 4809279 (1989-02-01), Kim
patent: 4849978 (1989-07-01), Dishon

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