Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1999-09-09
2001-01-30
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230040, C345S519000, C345S519000
Reexamination Certificate
active
06181632
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory device, and a writing method and a reading method, and more particularly relates to a memory device for, for example, obtaining an image data consisting of a desired number of pixels in the horizontal direction and vertical direction respectively without using a line memory for temporarily storing the image data of required number of lines, and a writing method and reading method of the memory device.
2. Description of Related Art
In image processing such as motion detection, for example, in MPEG (Moving Picture Experts Group), which is a standard for coding/decoding of image, a current frame is compared with a temporally precedent (past) or temporally subsequent (future) frame for processing.
FIG. 12
shows such an exemplary structure of a conventional image processing device. In the image processing device, when a pixel of the current frame is addressed, prescribed processing such as motion detection is performed by use of the pixel data in an area of 48 pixels×48 lines having the pixel of the precedent frame corresponding to the addressed pixel of the current frame at the center. The area which is required to perform the prescribed processing of the addressed pixel (herein 48 pixels×48 lines) is referred to as necessary area hereinafter.
The pixel data which is a component of the digital image data which is a dynamic image is supplied successively to, for example, a frame memory
101
having a one frame memory capacity, and stored, for example, in the order of line scanning. The pixel data stored in the frame memory
101
is read out successively in the order of line scanning and supplied to a line memory unit
102
.
The lime memory unit
102
comprises line memories of the number equal to the number of lines of the necessary area −1 namely 47 line memories
102
1
to
102
47
to acquire the pixel data loaded on the lines of the necessary area (herein, 48 lines), and the pixel data from the frame memory
101
is supplied to and stored in the line memory
102
. The pixel data stored in the line memory
102
is shifted to the right every time when the pixel data is supplied successively. Addressing on a certain pixel data, when the addressed pixel data is supplied to the line memory
102
1
and then one line pixel data is supplied, the addressed pixel data is sent out from the line memory
102
1
, and supplied to the next line memory
102
2
.
As in the line memory
102
1
, in the line memory
102
2
, the pixel data supplied from the line memory
102
2
is supplied to the next line memory
102
3
with one line delay. Similarly, in the following line memories
102
3
to
102
47
, the pixel data is supplied to the next line memory with one line delay respectively.
The pixel data sent out from the frame memory
101
is supplied not only to the line memory unit
102
but also to a two-dimensional parallel array
103
. The two-dimensional parallel array
103
consists of the same number of registers as the number of vertical and horizontal pixels which are components of a necessary area, which registers are arranged in the vertical and horizontal directions, in other words, 48×48 registers are arranged respectively in the vertical direction and the horizontal direction, and the pixel data sent out from the frame memory
101
is supplied to and stored in the register of the first row and first column of the two-dimensional parallel array
103
. In the two-dimensional parallel array
103
, the pixel data stored in the register of the first row first column is shifted to the next right register every time when the next pixel data is supplied successively, and at last the pixel data is deleted after the pixel data is stored in the 48-th column register (when the pixel data stored in the 47-th column register is shifted to the 48-th column register, the pixel data which has been stored in the 48-th column register is erased).
The pixel data sent out from the line memory
102
1
is supplied not only to the next line memory
102
2
but also to the two-dimensional parallel array
103
. In the two-dimensional parallel array
103
, the pixel data from the line memory
102
1
is supplied to and stored in the register of the second row first column. The pixel data stored in the register of the second row first column is shifted to the next right register successively every time when the next pixel data is supplied from the line memory
102
, and deleted after stored in the register of the 48-th column.
Respective pixel data sent out from the line memories
102
2
to
102
47
are supplied to the two-dimensional parallel array
103
, and in the two-dimensional parallel array
103
, the respective pixel data from the line memories
102
2
to
102
47
are supplied to and stored in the respective registers of the third row first column to the48-th row first column. The respective pixel data stored in the registers of the third row first column to the 48-th row first column are shifted successively to the right registers every time when the next data are supplied from the line memories
102
2
to
102
47
, and deleted after stored in the 48-th column registers.
On the other hand, the pixel data which is supplied to the frame memory
101
is supplied also to a line memory
106
. In the line memory
106
, the input pixel data is one line delayed and supplied to an image processing circuit
105
.
In the image processing device shown in
FIG. 12
, the pixel data is read out from the frame memory
101
at the starting so that, at the time when the pixel data of the current frame a is supplied to the image processing circuit
105
, the pixel data of 48 pixels×48 lines of pixels of precedent one frame corresponding to the pixel data of the current frame is stored in the 48×48 registers of the two-dimensional parallel array
103
, therefore, when a certain pixel data is supplied to the image processing circuit
105
, the pixel data in the necessary area for the pixel data is stored.
A pixel selector
104
selects the partial pixel data to be used in the image processing circuit
105
for processing of the pixel data supplied to the image processing circuit
105
from among the pixel data in the necessary area stored in the two-dimensional parallel array
103
as required, and supplies the selected pixel data to the image processing circuit
105
.
The image processing circuit
105
performs the predetermined processing to detect the motion by use of the pixel data from the line memory
106
and the pixel data from the image selector
104
, and sends out the processing result.
Because the respective pixel data of the current frame is processed by use of the pixel data of the precedent frame in the image processing device shown in
FIG. 12
, the respective pixel data of the next frame is processed by use of the pixel data of the current frame after the pixel data of the current frame has been processed. Accordingly the pixel data of the current frame is supplied to the frame memory
101
after the pixel data of the precedent frame is stored, it is required to store the pixel data of the current frame in the frame memory
101
to process the pixel data of the next frame.
However, because the pixel data of the precedent frame stored in the address where the pixel data of the current frame is stored is erased when the pixel data of the current frame is stored in the frame memory
101
, the pixel data of the precedent frame can not be used to process the pixel data of the current frame unless any counter measure is applied.
To avoid such problem, the line memory
102
is provided in the image processing device shown in
FIG. 12
, and the real time processing of image is made possible by retaining the lines of the number equal to the number of lines of the necessary area −1 in the line memory unit
102
.
However, in view of structuring the image processing device shown in
FIG. 12
in one chip (LSI (Large Scale Integration)), it is required to provide the line memory unit
102
, which
Fujiwara Takayoshi
Kondo Tetsujiro
Okumura Akihiro
Elms Richard
Frommer William S.
Frommer & Lawrence & Haug LLP
Nguyen Hien
Sony Corporation
LandOfFree
Multiple memory bank device and method for image processing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple memory bank device and method for image processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple memory bank device and method for image processing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2469488