Multiple match detection logic and gates for content...

Details Multiple match detection logic and gates for content... Multiple match detection logic and gates for content...

2005-02-22

2005-02-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189110

Reexamination Certificate

active

06859378

ABSTRACT:
Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including log2N stages of 2-to-1 multiple match gates, where N=2kand k is a positive integer. The final MMF is set to an active level whenever at least two of the input match signals indicate a match condition and the AMF is set to an active level whenever at least one of the input match signals indicates a match condition.

REFERENCES:
patent: 5748070 (1998-05-01), Priebe et al.
patent: 5852569 (1998-12-01), Srinivasan et al.
patent: 6044005 (2000-03-01), Gibson et al.
patent: 6137707 (2000-10-01), Srnivasan et al.
patent: 6175513 (2001-01-01), Khanna
patent: 6175514 (2001-01-01), Henderson et al.
patent: 6195277 (2001-02-01), Sywyk et al.
patent: 6243281 (2001-06-01), Pereira
patent: 6301636 (2001-10-01), Schultz et al.
patent: 6307798 (2001-10-01), Ahmed et al.
patent: 6317350 (2001-11-01), Pereira et al.
patent: 6362993 (2002-03-01), Henderson et al.
patent: 6392910 (2002-05-01), Podaima et al.
patent: 6480406 (2002-11-01), Jin et al.
patent: 6490650 (2002-12-01), Pereira
patent: 6493793 (2002-12-01), Pereira et al.
patent: 6499081 (2002-12-01), Nataraj et al.
patent: 6687785 (2004-02-01), Pereira
patent: 6697912 (2004-02-01), Akkary
patent: 6707694 (2004-03-01), Regev
patent: 6717876 (2004-04-01), Vlasenko et al.
patent: 6718433 (2004-04-01), Pereira
patent: 6728124 (2004-04-01), Ichiriu et al.
patent: 20030005146 (2003-01-01), Miller et al.
patent: 20030145178 (2003-07-01), Jiang
patent: 20040015652 (2004-01-01), Park et al.
Miller et al., “Content Addressable Memory Array Having Flexible Priority Support,” U.S. Appl. No. 09/884,797, filed Jun. 18, 2001.

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