Multiple match detection circuit and method

Details Multiple match detection circuit and method Multiple match detection circuit and method

2007-11-20

2007-11-20

Pham, Ly Duy (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050, C365S189070, C365S191000, C711S108000, C711S128000

Reexamination Certificate

active

11459420

ABSTRACT:
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.

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