Multiple location repair word line redundancy circuit

Details Multiple location repair word line redundancy circuit Multiple location repair word line redundancy circuit

1996-12-17

1998-06-30

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057744718

ABSTRACT:
A multi-location word line repair circuit is described that can be employed in a static memory including a plurality of sub-arrays responsive to respective sets of global word lines (GWL). Included in the repair circuit is a redundant word line (WL) decoder that stores and subsequently decodes the address of a defective global word line to be repaired. A selector circuit coupled to the redundant WL decoder is activated whenever the decoder decodes the stored address of the defective GWL from the memory address lines. When this occurs, the selector circuit activates at least one redundant global word line to repair the defective global word line within a selected group of global word lines that can include any combination of the respective sets of GWLs that are provided to the plurality of sub-arrays. To prevent the defective GWL from interfering with a memory operation being performed by the substitute RWL, a deselector circuit disables the defective global word line within the selected group of word lines.

REFERENCES:
patent: 5563820 (1996-10-01), Wedo et al.
patent: 5579326 (1996-11-01), McClure

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