Multiple line framer engine

Details Multiple line framer engine Multiple line framer engine

1997-07-31

2001-12-18

Marcelo, Melvin (Department: 2663)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S540000

Reexamination Certificate

active

06331988

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of telecommunications and in particular, to a single framer engine which frames multiple lines simultaneously.
BACKGROUND OF THE INVENTION
In telecommunications, the standard for digital transmission is a T1 line. The T1 digital transmission link has a capacity of 1.544 Mps in North America and a capacity of 2.048 Mps elsewhere. The T1 digital transmission link normally handles 24 voice conversations, each one digitized at 64 Kbps. That is, the 24 voice channels are sampled at an 8 kHz rate, with 8 bits per sample. In the telecommunications field, each 8 bit conversation sample is termed digital service, level 0 or DS0. The 24, 8 bit samples are time division multiplexed together to form a digital service, level 1 or DS1.
In general, a frame is a logical transmission unit which has a defined format so that the receiving equipment can recognize the meaning and purpose of the specific bits. Frames usually contain their own control information for addressing and error checking. In telecommunications, a frame or a DS 1 frame is a sample of all 24 channels plus a synchronization bit called a framing bit. The framing bit has an identifiable data sequence patterned thereon to identify individual time slots within the time division multiplexed frame. As such, each frame has a block length of 193 bits (i.e., 24×8+1). Specifically, the first bit is a frame overhead bit, while the remaining bits are available for data or payload. Frames are transmitted at a rate of 8 kHz, thus creating the 1.544 Mps transmission rate of a North American T1 digital transmission link.
In telecommunications, two well known framing formats are the superframe and the extended superframe formats. The superframe transmission format consists of 12 DS1 frames, i.e., it has 12 separate 193 bit frames equaling 2316 bits. As stated above, the first bit position is the frame overhead bit position and is used for the frame and signaling phase alignment. The extended superframe transmission format groups together 24 DS1 frames as opposed to the 12 in the superframe format. Since the 12 positions in the superframe format (or 24 bits in the extended superframe format) do not necessarily fall in the right sequential order, there is a need to identify then from within the data stream. This is the objective of the framer.
In general, a framer engine operates on one DS1 signal at a time. The entire DS1 data stream is loaded into memory and then the framer processor examines the memory to determine where the framing pattern is. However, there is currently a growing demand to frame up simultaneously on four DS1 lines in a single framer engine. In addition, this demand may extend to frame up to eight or more DS1 lines in a single framer. The prior art framers utilize a shifter based approach, which in terms of computational functionality is feasible. A major drawback of this approach is that it operates on one DS1 signal at a time and as a result requires four single framers to operate on four DS1 lines. Specifically, the shifter based approach utilizes long shift registers to search for a particular framing bit pattern. The search mechanism looks at every 193rd bit in a superframe or every 772nd bit in an extended superframe and taps/offsets to the appropriate location until a correct successive pattern found. A drawback of this approach is that it is completely hardwired and uses a large number of logic gates. This in turn utilizes a large silicon area which could have been used for other functionality. As such, although prior art systems are computationally feasible, it is at a high cost.
Accordingly, there is a need to provide a simple and efficient framer engine structure and method which accommodates multiple DS1 lines at competitive costs.
SUMMARY OF THE INVENTION
The present invention teaches a structure and a method for simultaneously framing up data of multiple DS1 lines onto a single framer engine. The framer engine is employable with standard transmission formats. Importantly, the present invention tracks and exploits technological advances in random access memory development without expensive modification to the framer engine.
In an exemplary embodiment of the present invention, input data is pre-aligned and stored onto a memory structure, such as a random access memory. A recognition or comparison unit then performs the recognition of the framing bit sequence. The present invention provides memory configurations for all of the standard transmission formats so that the input data is properly pre-aligned prior to the recognition processing. Importantly, the present invention design occupies a smaller amount of the silicon block as compared to a long shifter.
Advantageously, the structure and method of the present invention is utilizable with any number of DS1 lines. The above factors make the present invention a cost effective and efficient device for simultaneously framing multiple DS1 lines with a single framer engine configuration.


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“DSP based architecture for real-time T1 bandwidth Management and Control” appeared in IEEE Communications, 1990 ICC '90, Including Supercomm Technical Sessions. Supercomm/ICC '90. Conference Record., IEEE International Conference on , pp. 690-697 vol. 2.*
IEL/IEC ref numbers for the citation above are: CH2829-0/90/0000-0690. The Conference was Held Apr. 16-19, 1990. 4 pages total (vol. XXX+1759).

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