Multiple level RAM device

Details Multiple level RAM device Multiple level RAM device

2002-11-26

2004-10-05

Elms, Richard (Department: 2824)

Static information storage and retrieval

Analog storage systems

C365S189011, C365S189080, C365S185030

Reexamination Certificate

active

06801445

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a multiple level logic, memory device, and more particularly, to a multiple level logic, dynamic RAM device and methods to read and write such a device.
(2) Description of the Prior Art
Memory devices are a critical component in modern electonics systems. Nonvolatile memories, static memories, and dynamic memories are some of the more popular forms. Typical memory systems store data as binary bits of information. Each memory cell is typically configured to store a digital data bit representing a ‘0’ or a ‘1’ value. If, for example, the memory technology is a nonvolatile device, then the storage mechanism is the threshold voltage of the nonvolatile transistor. A ‘0’ value is stored when the threshold voltage is low while a ‘1’ value is stored when the threshold voltage is high. Such digital systems are termed binary because the data bits can take one of only two possible values: ‘0’ or ‘1’.
Referring now to
FIG. 1
, a prior art, binary level logic, memory device is shown. In this example, the memory technology is a dynamic RAM, or DRAM. An individual DRAM cell, cell i,
10
is shown. This cell
10
is one of a large array of cells that make up the DRAM device. In the DRAM cell
10
, the cell memory state is represented by the charge stored on a cell capacitor C
CELL
18
. The DRAM cell
10
may be accessed for reading or writing. Typically, memory cells are grouped into bytes (8 bits) or words (16 bits) that are accessible in a single read/write cycle. However, to simplify the schematic, only a single bit, or cell
10
, is shown.
To access the cell i
10
for writing, the address of the cell is set on the external address bus A
0
-A
n
34
. The data value D
x
38
of the cell
10
is set on the external data bus. The decoder block
26
of the memory device selects the specific cell i
10
based on the address value A
0
-A
n
34
. The data value D
x
38
is then routed to cell i
10
as the voltage signal V
i
22
. In a typical arrangement, the decoder
26
activates a specific word line, not shown, to turn on an access transistor, not shown. The voltage signal V
i
22
is then forced onto a specific bit line to effectively couple V
i
22
to C
CELL
14
.
The stored data state of cell i
10
is read in a similar fashion. To read cell i
10
, the external address value A
0
-A
n
34
is used by the encoder block
30
to select cell i
10
. Once again, a particular word line is asserted to activate an access transistor, not shown. The charge stored on C
CELL
14
is then accessible through the sharing voltage V
ie
42
. A sense amp
46
is used to detect the state, ‘0’ or ‘1’, of cell I
10
and to generate the correct data value D
x
38
.
Several observations can now be made concerning the prior art memory device. First, the system is binary. The only allowed values for D
x
38
are ‘0’ and ‘1’. D
x
38
is translated into a storage voltage V
i
22
comprising one of two possible voltages, 0 Volts and VDD. Second, because the system is binary, every bit of data stored in the memory array requires one cell
10
. Therefore, a 2 Megabit memory requires 2 Megabits of cells. Third, if the memory density of the device is to increase, most of the effort must focus on reducing the size of each cell and the size of the routing overhead associated with decoding and encoding. It would advantageous to be able to increase memory density without increasing the number of cells.
Several prior art inventions describe class D amplifiers. U.S. Pat. No. 6,084,797 to Maloberti describes a method to read a multiple logic level, non-volatile memory cell. The approach forces a sequence of currents through a selected cell drain and then measures the voltage to determine the stored value. U.S. Pat. No. 6,069,830 to Seo discloses a circuit and a method to determine the value stored in a multiple level logic, nonvolatile memory device. Drain current is forced into a selected cell and the word line voltage is sequenced until the drain current matches a reference value. U.S. Pat. No. 5,673,221 to Calligaro et al describes a circuit and a method to read a multiple level logic, nonvolatile memory cell. The approach uses a current comparitor to determine the cell threshold.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable multiple level logic, memory device.
A further object of the present invention is to provide an effective method to read and write a multiple level logic, memory device.
Another further object of the present invention is to provide a multiple level logic, memory device wherein the memory cell technology is dynamic RAM.
A still further object of the present invention is to provide a multiple level logic, memory device that provides increased data storage per unit area.
In accordance with the objects of this invention, a multiple level logic memory device is achieved. The device comprises, first, a plurality of memory cells capable of storing an analog voltage. Second, there is included a means of converting an external data word value comprising one value of a set of at least three possible values into a writing analog voltage corresponding to the external data word value. Third, a means of decoding an external address value in response to a write command such that the writing analog voltage is electrically coupled to the memory cell is included. Fourth, there is included a means of converting the memory cell analog voltage into an external data word value comprising one value of the set of at least three possible values corresponding to the memory cell analog voltage. Finally, a means of encoding the external address value in response to a read command such that the memory cell analog voltage is electrically coupled to the means of converting the memory cell analog voltage is used.
Also in accordance with the objects of this invention, a method to write data into a multiple level logic memory is achieved. The multiple level memory device comprises a plurality of memory cells capable of storing an analog voltage. The method comprises, first, converting an external data word value comprising one value of a set of at least three possible values into a writing analog voltage corresponding to the external data word value. Last, an external address value is decoded in response to a write command such that the writing analog voltage is electrically coupled to a memory cell.
Also in accordance with the objects of this invention, a method to read data from a multiple level logic memory device is achieved. The multiple level logic memory device comprises a plurality of memory cells capable of storing an analog voltage. The method comprises, first, encoding an external address value in response to a read command such that an analog voltage of the memory cell is electrically coupled to a means of converting the memory cell analog voltage. Last, the memory cell analog voltage is converted into an external data word value comprising one value of a set of at least three possible values corresponding to the memory cell analog voltage.


REFERENCES:
patent: 3705391 (1972-12-01), Baker
patent: 5459686 (1995-10-01), Saito
patent: 5479170 (1995-12-01), Cauwenberghs et al.
patent: 5559734 (1996-09-01), Saito
patent: 5673221 (1997-09-01), Calligaro et al.
patent: 5808932 (1998-09-01), Irrinki et al.
patent: 5847991 (1998-12-01), Tong et al.
patent: 6069830 (2000-05-01), Seo
patent: 6084797 (2000-07-01), Maloberti et al.
patent: 6094368 (2000-07-01), Ching
patent: 1486912 (1974-09-01), None
patent: 52004746 (1977-01-01), None

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