Multiple level programming in a non-volatile memory device

Details Multiple level programming in a non-volatile memory device Multiple level programming in a non-volatile memory device

2007-05-01

2007-05-01

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185030

Reexamination Certificate

active

11067977

ABSTRACT:
The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory block. The upper page of the memory block is then programmed.

REFERENCES:
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patent: 6278632 (2001-08-01), Chevallier
patent: 6522580 (2003-02-01), Chen et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 6967872 (2005-11-01), Quader et al.
patent: 2004/0170056 (2004-09-01), Shibata et al.
K. Takeuchi et al.; A Multiple Cell Architecture for High-Speed Programmable Multilevel NAND Flash Memories; IEEE Journal Of Solid-State Circuits, vol. 33, No. 8, Aug. 1998; pp. 1228-1238.

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