Multiple level minimum logic network

Details Multiple level minimum logic network Multiple level minimum logic network

2004-06-16

2008-09-16

Nguyen, Brian D (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S258000, C709S238000

Reexamination Certificate

active

07426214

ABSTRACT:
A network or interconnect structure100utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes102in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components104and improving speed performance of message communication.

REFERENCES:
patent: 5684959 (1997-11-01), Bhat et al.
patent: 5715251 (1998-02-01), Du
patent: 5737320 (1998-04-01), Madonna
patent: 5781551 (1998-07-01), Born

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