Multiple level minimum logic network

Details Multiple level minimum logic network Multiple level minimum logic network

1995-07-21

1999-11-30

An, Meng-Ai T.

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

709239, 709240, G06F 1300

Patent

active

059960205

ABSTRACT:
A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a "deflection" or "hot potato" system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication.

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