Multiple level conductor wordline strapping scheme

Details Multiple level conductor wordline strapping scheme Multiple level conductor wordline strapping scheme

1997-06-27

2000-08-08

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257759, 257760, 257774, 257775, 257309, 257315, H01L 2348, H01L 2352, H01L 2940

Patent

active

061005886

ABSTRACT:
A semiconductor memory device includes an array of storage cells, each cell having a transfer transistor with a gate electrode. A separate wordline 32 interconnects the gate electrodes of each row of the storage cells. A first conductive layer includes stripes 38, each stripe overlying a different row of the storage cells and connecting to the wordline and the gate electrodes of the storage cells of a different odd numbered row of the storage cells. An insulator surrounds the stripes of the first conductive layer. A second conductive layer, separated from the stripes of the first conductive layer by the insulator, includes stripes 39, each stripe of the second conductive layer overlying a different even numbered row of storage cells and connecting to the wordline and the gate electrodes of the different even numbered row of storage cells. This arrangement reduces parasitic delay caused by the wordlines in a high density memory and increases the minimum pitch between stripes of any one level of conductor layer.

REFERENCES:
patent: 5055898 (1991-10-01), Beilstein, Jr. et al.
patent: 5177027 (1993-01-01), Lowery et al.
patent: 5671175 (1997-09-01), Liu et al.
patent: 5707884 (1998-01-01), Fontanna et al.

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