Multiple layer electrode structure for semiconductor device and

Details Multiple layer electrode structure for semiconductor device and Multiple layer electrode structure for semiconductor device and

1991-11-05

1992-12-29

Thomas, Tom

Fishing, trapping, and vermin destroying

437 41, 437 44, 437162, 437192, 437200, 437228, 437233, H01L 2170

Patent

active

051751186

ABSTRACT:
A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystaline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and ethcing the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.

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Neues aus der Technik, No. 4 vom 15, Aug. 15, 1983 (German).
IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun. 1985, pp. 26-27.
Huang et al., "A MOS Transistor with Self-Aligned Polysilicon Source-Drain", IEEE Electron Device Letters, vol. EDL-7, No. 5, May 1986, pp. 314-316.

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