Multiple layer electrical interface

Details Multiple layer electrical interface Multiple layer electrical interface

1999-03-15

2001-07-03

Paladini, Albert W. (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S261000, C174S266000, C361S778000, C361S795000, C257S698000

Reexamination Certificate

active

06255602

ABSTRACT:

This invention relates generally to a multiple layer electrical interface for testing semiconductors and integrated circuits, and more particularly to a universal interface which may be mass produced and then customized for a particular semiconductor device or integrated circuit.
BACKGROUND OF THE INVENTION
Printed circuit boards are manufactured by creating an artwork and etching copper away from the non-current carrying portions of the board. This process is non-reversible; hence, once the printed circuit board is etched it is then customized or “dedicated” to a certain semiconductor device/integrated circuit and cannot be changed without modification of the artwork and re-fabrication of the printed circuit board.
One particular use of printed circuit boards is that of an interface or interconnection device known as a “space transformer” for connecting a vertical pin integrated circuit probing device to the integrated circuit test equipment. As the number and density of connection pads increase on integrated circuits, special multiple probe devices have been devised for holding the probes in a predetermined pattern corresponding to the integrated circuit to be tested, and slidably supporting the probes, which are constructed as vertical pins. The test device is moved against the bottom ends of the probe pins while contact is maintained with the exposed upper heads of the pins. The type of probe head thus constructed was developed by IBM and is described in a number of U.S. Patents including, for example, U.S. Pat. No. 3,806,801 describing an earlier construction, and U.S. Pat. No. 4,027,935. This type of probe holder, which is sometimes referred to as a vertical-pin integrated circuit probing device and sometimes as a hybrid buckling beam probe has been improved by IBM and other manufacturers. Such a device is manufactured and sold by applicant's assignee as a COBRA® probe, and is used in conjunction with a printed circuit test board, which is connected in test circuit relationship with the external test equipment for testing the integrated circuit.
Inasmuch as the matrix or pattern of exposed heads of the vertical-pin probes is relatively small and dense, and must be connected to a larger pattern of traces (PCB traces) on the printed circuit test board, an interconnection device commonly known as a “space transformer” is generally employed. Various types of space transformers are shown in the prior art, for example in U.S. Pat. No. 4,038,599 issued Jul. 26, 1977 to Bove et al., U.S. Pat. No. 3,654,585 issued Apr. 4, 1972 to Wickersham, U.S. Pat. No. 3,911,361 issued Oct. 7, 1975 to Bove et al., and U.S. Pat. No. 4,901,013 issued Feb. 13, 1990 to Benedetto et al. A common type of prior art space transformer comprises a wired interface used together with an etched “dedicated” printed circuit board is depicted in
FIGS. 1
a
and
1
b
of the present application.
The prior art drawings of
FIG. 1
a
and
FIG. 1
b
schematically illustrate a silicon wafer
10
having a number of integrated circuit devices thereon with contact pads
12
to be probed. Multiple power, ground and signal potentials are supplied from test equipment through connectors
14
to “pogo pads” on the outer periphery of a printed circuit board
16
. A particular pattern of test circuit dedicated to a particular pattern of contact pads
12
on the integrated circuit device is provided by means of traces
18
etched into or deposited on the printed circuit board. A second set of wire leads
20
connected to the etched traces
18
terminate on the underside of board
16
, so as to make contact at
19
with the upper ends of probe pins
22
held in a probe assembly
24
.
While the simple construction of
FIGS. 1
a
and
1
b
may have been adequate for integrated circuit devices in the past, the complexity of the test circuits and density of the devices on the silicon wafer has greatly challenged the probe card manufacturer. As the probe card designs become more complex, they become more expensive. Once dedicated to a particular integrated circuit, they can no longer be used if the integrated circuit is modified.
It is known that complex circuit designs can be simplified by using multiple layer printed circuit boards in which, for example, multiple layers of conductive traces are interposed between insulating layers and used to carry the signal, power and ground paths. In order to reach the internal layers, conductors passing through the insulating layers, known as “vias” are used. Pin count or number of input/outputs (I/O) are increasing as each generation of semiconductor device/integrated circuit is introduced into the marketplace. Testers are introduced into the market with higher pin count capability in order to keep pace with the increased I/O of semiconductor devices. Most of these testers increase pin count in binary increments. The number of vias and the layout of these vias are also done on the basis of incremental binary additions.
Example: A new tester is introduced into the marketplace. The new tester is capable of 1024 signals in addition to all required power supplies and grounds. The older generation of testers may have been capable of 512 signals and required power supplies and grounds. The new tester dictates that the layout of vias must now be capable of routing 1024 signals rather than 512 signals and therefore the printed circuit must be capable of routing any of 1024 signals to any of 1024 pin locations.
Another problem is encountered with providing the conductive path from the trace on the top side of a printed circuit board to a location on the underside of the printed circuit board which corresponds to a contact pad on the silicon wafer. The prior art carried out this transition by means of separate wires (see reference number
20
in
FIGS. 1
a
and
1
b
). Constructing an interface in this manner becomes extremely expensive when the number of contact pads on the device increases. Various suggestions to effect the space transformation have been proposed in the prior art, including a laminated interface proposed in co-pending application Ser. No. 09/186,084 in the names of A. P. Martel and F. T. McQuade filed Nov. 5, 1998 and assigned to the present assignee.
The aforementioned space transformer designs require a separate member to be attached to the center of the printed circuit board, and provision made for a conductive path between the trace termination on the printed circuit board to the underside of the board. The conductive path terminates at a pin location in a contact pattern or “footprint”, where contact is made with the probe pins of the probe assembly. It would be desirable to simplify the process for running the final conductive path to the footprint or probe pin contact location.
Accordingly, one object of the present invention is to provide an improved multiple layer electrical interface for testing semiconductors and integrated circuits.
Another object of the invention is to provide an improved method of manufacturing an electrical interface and space transformer for use with vertical pin probe devices.
Another object of the invention is to reduce the cost associated with converting from one pin-out configuration to another when testing integrated circuits.
Another object of the invention is to reduce the cost of increasingly complex test circuit designs on a printed circuit probe card.
SUMMARY OF THE INVENTION
Briefly stated, a universal design of a multiple layer printed circuit board, incorporates a series of routing vias interconnecting the various layers. The routing vias are connected to conductive traces in the internal trace layers by internal junctions. The internal junctions are located on the via so that internal junctions may be selectively severed by means of a laser or high pressure water cutting system or other fine line cutting tool or mechanism to customize the circuit design for a particular semiconductor device or integrated circuit.
The improved electrical interface comprises a multiple layer, universally connected and selectively disconnectable cir

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