Multiple latched accumulator fractional N synthesis

Details Multiple latched accumulator fractional N synthesis Multiple latched accumulator fractional N synthesis

1990-08-31

1991-12-03

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 16, 331 25, 332127, 375120, 377 48, 455 76, 455183, 455260, H03C 309, H03L 7197

Patent

active

050703102

ABSTRACT:
A multiple latched accumulator fractional-N synthesizer for use in digital radio transceivers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The carry outputs of each accumulator are coupled through delays (645, 647, 649, 631, 633) equal to one less delay than the number of accumulators and added (635) such that all higher order accumulator carry outputs add to a net summation of zero so as to not upset the desired fractional setting of the first accumulator.

REFERENCES:
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patent: 4609881 (1986-09-01), Wells
patent: 4758802 (1988-07-01), Jackson
patent: 4800342 (1989-01-01), Jackson
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patent: 4815018 (1989-03-01), Reinhardt et al.
patent: 4816774 (1989-03-01), Martin
Brewerton et al., "Defining the Elements of Good Design", Microwaves and RF, Jun. 1984, pp. 79-85, 124.

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