Multiple interrupt microprocessor system

Details Multiple interrupt microprocessor system Multiple interrupt microprocessor system

1974-10-30

1977-01-18

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 918

Patent

active

040042839

ABSTRACT:
A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. The digital system uses a multi-level interrupt circuit arrangement including a masked interrupt request input responsive to a multi-plexed interrupt request from peripheral circuits of the system and a non-masked interrupt request input which activates circuitry internal to the microprocessor chip for bypassing program control in initiating an interrupt sequence.

REFERENCES:
patent: 3286239 (1966-11-01), Thompson
patent: 3290658 (1966-12-01), Callahan
patent: 3386082 (1968-05-01), Stafford
patent: 3419852 (1968-12-01), Marx
patent: 3742457 (1973-06-01), Calle
patent: 3825902 (1974-07-01), Brown
patent: 3828325 (1974-08-01), Stafford

Affiliated with

Also associated with

Rating

Multiple interrupt microprocessor system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple interrupt microprocessor system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple interrupt microprocessor system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-75943