Multiple interconnected ring oscillator circuit

Oscillators – Ring oscillators

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331 25, 331 1A, 331 74, 331 2, 331 45, 327158, 327156, 327157, H03B 2700

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054753449

ABSTRACT:
An array oscillator circuit is disclosed herein. The array oscillator circuit includes a plurality of ring oscillators, each ring oscillator having a plurality of buffer stages for generating output signals on a like plurality of oscillator output ports. Interconnections are provided between each of the plurality of ring oscillators and at least one other of the plurality of ring oscillators such that the plurality of ring oscillators oscillate at identical frequencies and such that the output signals on the each ring oscillator's plurality of oscillator output ports have a phase offset from the signals generated on corresponding ones of the other ring oscillator's oscillator output ports. A multiplexer provides an electrical connection to a selected one of the plurality of oscillator output ports of the plurality of ring oscillators.

REFERENCES:
patent: 5268656 (1993-12-01), Muscavage
patent: 5347234 (1994-09-01), Gersbach et al.
"Wide Range, Variable-Frequency Oscillator Circuit" IBM Tech. Disclosure, vol. 30, No. 3, Aug. 1987 pp. 1181-1182.
James A. Gasbarro and Mark A. Horowitz, "A Single-Chip, Functional Tester for VLSI Circuits," 1990 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 84-85.
Ian A. Young, Jeff K. Greason, Jeff E. Smitt and Keng L. Wong, "A PLL Clock Generator with 5 to 110 MHz Lock Range for Microprocessors," 1992 IEEE International Solid-State Circuits Conference, pp. 50-51.

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