Multiple instruction set mapping

Details Multiple instruction set mapping Multiple instruction set mapping

1994-09-19

1996-10-22

Geckil, Mehmet

Boots, shoes, and leggings

395375, 364DIG1, 364258, 3642599, 3642318, 3642379, G06F 900

Patent

active

055686460

ABSTRACT:
A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction pipeline 6. As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruction words of the first instruction set. The second instruction set has program instruction words of a smaller bit size than those of the first instruction set and is a subset of the first instruction set. Smaller bit size improves code density, whilst the nature of the second instruction set as a subset of the first instruction set enables a one-to-one mapping to be efficiently performed and so avoid the need for a dedicated instruction decoder for the second instruction set.

REFERENCES:
patent: 4274138 (1981-06-01), Shimokawa
patent: 4839797 (1989-06-01), Katori et al.
patent: 5392408 (1995-02-01), Fitch
patent: 5475824 (1995-12-01), Grochowski et al.
patent: 5481684 (1996-01-01), Richter et al.
patent: 5524211 (1996-06-01), Woods et al.

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