Multiple instruction decoder for minimizing register port requir

Details Multiple instruction decoder for minimizing register port requir Multiple instruction decoder for minimizing register port requir

1989-06-06

1992-07-07

Lee, Thomas C.

Boots, shoes, and leggings

3642386, 3642398, 3642405, 3642624, 3642628, 3642629, 3642318, 3642474, 3642476, 3642426, 3642419, 364DIG1, 395725, G06F 930, G06F 934, G06F 938, G06F 1202

Patent

active

051290677

ABSTRACT:
A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand identifiers for M available read ports (where M is less than N) based on arbitration data corresponding to each of the logic instructions, and for generating control signals indicative thereof; and a multiplexing unit for selectively supplying the N register-operand identifiers to the M available read ports in response to the control signals generated by the arbitration logic.

REFERENCES:
patent: 4443848 (1984-04-01), Gehman
patent: 4473880 (1984-09-01), Budde et al.
patent: 4488217 (1984-12-01), Binder et al.
patent: 4604683 (1986-08-01), Russ et al.
patent: 4764866 (1988-08-01), Downey

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